The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL
Title
: 
The RTL design of 32-BIT 5- stage pipeline risc processor using verilog HDL

Personal Author
: 
Lim, Jonie Joo Nee, 1978-

Publication Information
: 
2008

Physical Description
: 
xiv, 77 p. : ill. ; 30 cm.

General Note
: 
Also available in CD-ROM : CP 017450 ra
 
Supervisor : Prof. Dr Mohamed Khalil Mohd. Hani

Subject Term
: 
Reduced instruction set computers

Added Author
: 
Mohamed Khalil Mohd. Hani,

Added Corporate Author
: 
Fakulti Kejuruteraan Elektrik

Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik)) - Universit Teknologi Malaysia, 2008


LibraryItem BarcodeCall NumberMaterial TypeItem Category 1
FKE LibraryFKE30000002738QA76.5 L55 2008 rafClosed Access ThesisUTM Master Thesis (Closed Access)
Perpustakaan Raja Zarith Sofiah30000010143497QA76.5 L55 2008 rafClosed Access ThesisUTM Master Thesis (Closed Access)