VHDL modelling and asic design of a shortest-path processor core for network routing
Title
: 
VHDL modelling and asic design of a shortest-path processor core for network routing

Personal Author
: 
Teoh, Giap Seng

Publication Information
: 
Skudai : Universiti Teknologi Malaysia, 2003

Subject Term
: 
VHDL (Computer hardware description language)
 
Application specific integrated circuits -- Design and construction -- Data processing

Thesis (Master of Engineering (Electrical)) - Universiti Teknologi Malaysia, 2003


LibraryItem BarcodeCall NumberMaterial TypeItem Category 1
FKE LibraryFKE30000000784TK7885.7 T46 2003Closed Access ThesisUTM Master Thesis (Closed Access)
Perpustakaan Raja Zarith Sofiah30000010028034TK7885.7 T46 2003Closed Access ThesisUTM Master Thesis (Closed Access)
SPS LibrarySPS30000001088TK7885.7 T46 2003 rafClosed Access ThesisUTM Master Thesis (Closed Access)