The RTL design of 32-bit RISC processor using verilog HDL
Title
: 
The RTL design of 32-bit RISC processor using verilog HDL

Personal Author
: 
Hafizul Hasni Manab, 1987-

Publication Information
: 
2012

Physical Description
: 
xvii, 131 p. : ill. ; 30 cm.

General Note
: 
Supervisor :Assoc. Prof. Dr. Muhammad Nasir Ibrahim
 
Also available in CD-ROM : CP 028872 ra

Subject Term
: 
Reduced instruction set computers

Added Author
: 
Muhammad Nasir Ibrahim

Added Corporate Author
: 
Fakulti Kejuruteraan Elektrik

Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Sistem Mikroelektronik)) - Universiti Teknologi Malaysia, 2012


LibraryItem BarcodeCall NumberMaterial TypeItem Category 1
FKE LibraryFKE30000005050QA76.5 H34 2012 rafClosed Access ThesisUTM Master Thesis (Closed Access)
Perpustakaan Raja Zarith Sofiah30000010299111QA76.5 H34 2012 rafClosed Access ThesisUTM Master Thesis (Closed Access)