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Integrated circuits -- Testing
(25)
Digital integrated circuits -- Testing
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1. 
Cover image for Design, fabrication and testing of integrated circuits
2. 
Cover image for Testing for small-delay defects in nanoscale CMOS integrated circuits
3. 
Cover image for Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty
4. 
Cover image for Power supply voltage control testing technique as a novel electrical test strategy for analogue integrated circuits
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Cover image for Power supply voltage control testing technique as a novel electrical test strategy for analogue integrated circuits; Telechelic natural rubber oligomers via controlled ozonolysis; Symbolic manipulations related to certain aspects such interpretations of graphs; A study of vibrational power flow in fibre-reinforced plastic material; Ultrasound fields in crossflow microfiltration
6. 
Cover image for Automatic testing and evaluation of digital integrated circuits
7. 
Cover image for The effects of backdriving digital integrated circuits during in-circuit testing
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Cover image for Testability method at register transfer level (RTL) and gate level
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Cover image for Testability method at register transfer level (RTL) and gate level
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Cover image for Test vectors reduction for integrated circuit testing using horizontal hamming distance
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Cover image for Test vectors reduction for integrated circuit testing using horizontal hamming distance
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Cover image for Crystal growth and evaluation of silicon for VLSI and ULSI
13. 
Cover image for A model-based testing framework for trusted platform module
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Cover image for A model-based testing framework for trusted platform modul
15. 
Cover image for Digital system test and testable design : using HDL models and architectures
16. 
Cover image for Functional test generation using micro operation fault model
17. 
Cover image for Modified pattern generator of built-in self test for sequential circuits with reduced test time
18. 
Cover image for Accelerating test, validation and debug of high speed serial interfaces
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Cover image for Modified pattern generator of built-in self test for sequential circuits with reduced test time
20. 
Cover image for Functional test generation using micro operation fault model
21. 
Cover image for Test pattern generation for path delay fault using stuck-at fault automatic test pattern generator
22. 
Cover image for An engineer's guide to automated testing of high-speed interfaces
23. 
Cover image for Built-in self-test method at register transfer level design for finite impulse response filter, infinite impulse response filter and greatest common divisor calculator
24. 
Cover image for Built-in self-test method at register transfer level design for finite impulse response filter, infinite impulse response filter and greatest common divisor calculator
25. 
Cover image for Design of enhanced non exclusive XOR test of 2-D linear feedback shift register
26. 
Cover image for Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm
27. 
Cover image for Design of enhanced non exclusive XOR test of 2-D linear feedback shift register
28. 
Cover image for Power-aware system-on-chip test scheduling based on enhanced rectangle packing algorithm
29. 
Cover image for Software-based self-test with scan design at register transfer level for 16-bit RISC processor
30. 
Cover image for Software-based self-test with scan design at register transfer level for 16-bit RISC processor
31. 
Cover image for ESD : failure mechanisms and models
32. 
Cover image for Defects in microelectronic materials and devices
33. 
Cover image for Functional design errors in digital circuits : diagnosis correction and repair
34. 
Cover image for Test and diagnosis of analogue, mixed-signal and RF integrated circuits : the system on chip approach
35. 
Cover image for Nanometer technology designs : high quality delay tests
36. 
Cover image for RF measurements for cellular phones and wireless data systems
37. 
Cover image for Defect-oriented testing for nano-metric CMOS VLSI circuits
38. 
Cover image for Hardware and software, verification and testing : Second International Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, 2006 : revised selected papers
39. 
Cover image for Digital integrated circuits : design-for-test using Simulink and Stateflow
40. 
Cover image for The core test wrapper handbook : rationale and application of IEEE Std 1500
41. 
Cover image for Wireless IC testing on FPGA platform
42. 
Cover image for VLSI test principles and architectures : design for testability
43. 
Cover image for Data mining and diagnosing IC fails
44. 
Cover image for Applied formal verification
45. 
Cover image for Fault diagnosis of analog integrated circuits
46. 
Cover image for Functional verification of programmable embedded architectures : a top-down approach
47. 
Cover image for Introduction to advanced system-on-chip test design and optimization
48. 
Cover image for An experimental approach to CDMA and interference mitigation : from system architecture to hardware testing through VLSI design
49. 
Cover image for The e hardware verification language
50. 
Cover image for Testing of digital systems
51. 
Cover image for Elements of STIL : principles and applications of IEEE Std. 1450
52. 
Cover image for Photo-excited processes, diagnostics, and applications : fundamentals and advanced topics
53. 
Cover image for Verification by error modeling : using testing techniques in hardware verification
54. 
Cover image for CTL for test information of digital ICs
55. 
Cover image for Kajian sistem kerangka keluli dan teras konkrit bertetulang bangunan tinggi analisis unsur terhingga tidak lelurus
56. 
Cover image for IC test based on scan cell
57. 
Cover image for Design for testtability (DFT), based on ad-hoc philosphy
58. 
Cover image for Pembinaan dan penilaian sistem pengurusan rekod stor bengkel sekolah menengah teknik berasaskan web (SISTOR)
59. 
Cover image for Profil bentuk RPV yang optimum bagi misi pengawasan
60. 
Cover image for Rekabentuk sistem siaraya
61. 
Cover image for Design for at - speed test, diagnosis and measurement
62. 
Cover image for Machining of IC chips for failure analysis
63. 
Cover image for Random power supply as a test vector to expose soft defects in CMOS digital circuits
64. 
Cover image for IC test simulator (synthesis method)
65. 
Cover image for IC test simulator : boolean difference method
66. 
Cover image for Essentials of electronic testing for digital, memory and mixed - signal VLSI circuits
67. 
Cover image for System-on-a-chip : design and test
68. 
Cover image for IC test process simulation
69. 
Cover image for Penentuan gangguan peralatan telekomunikasi sistem digital gelombang mikro di Malaysia ... [et al.]
70. 
Cover image for Pengujian litar digital
71. 
Cover image for Pengujian litar digital ... [et al.]
72. 
Cover image for Hybrid microcircuit technology handbook : materials, processes, design, testing and production
73. 
Cover image for Reka bentuk untuk pengujian 2 ... [et al.]
74. 
Cover image for Reka bentuk untuk pengujian 2
75. 
Cover image for Using waves and VHDL for effective design and testing
76. 
Cover image for Feasibility study on ISSQ test as burn-in replacement for MC68HC11E9 device
77. 
Cover image for Using waves and VHDL for effective design and testing
78. 
Cover image for Feasibility study on ISSQ test as burn-in replacement for MC68HC11E9 device
79. 
Cover image for Multichip modules with integrated sensors
80. 
Cover image for Pengoptimuman dan kawalan penghantaran beban berekonomi; Jawi character recognition using artificial neural network; Industry standard digital multimeter; Merekabentuk dan membina satu model bandul elektrik kompaun; Voltage reference maintenance program; Merekabentuk pentafsir petri net pada komputer
81. 
Cover image for Principles of semiconductor network testing
82. 
Cover image for Circuit design and layout of digital encryption processor
83. 
Cover image for Designer's guide to testable asic devices
84. 
Cover image for Digital systems testing and testable design
85. 
Cover image for Design to test : a definitive guide for electronic design, manufacture, and service
86. 
Cover image for Design and test techniques for VLSI and WSI circuits
87. 
Cover image for Analisa terbantu komputer untuk motor elektrik : bahagian I; 6800-based digital circuit troubleshooting system in-circuit and board-level testing; C.A.D. for instrumentation : part I; Pembinaan dan pengawalan berkomputer bagi sebuah pedati; Rekabentuk terbantu komputer bagi instrumentasi; Rekabentuk makmal akustik tetap untuk Fakulti Kejuruteraan Elektrik Universiti Teknologi Malaysia Skudai; Kajian terhadap taburan voltan disepanjang penebat gantungan 275 kv apabila dicemari dengan hujan asid; Rekabentuk makmal akustik sementara blok B Universiti Teknologi Malaysia, Jalan Semarak, Kuala Lumpur
88. 
Cover image for Kaedah pernomboran dalam membandingkan kejayaan sistem pengesan terus dan pengesan jelas dalam sistem perhubungan optik; Pemprosesan imej digital; Penyelakuan sistem kawalan taklelurus dengan data tersampel; Point on wave switch; Model komputer untuk sistem perhubungan optik; MC6800 based programmable digital integrated circuit tester; Implementation of X.25 Datagram for a personal computer
89. 
Cover image for Pengujian IC digital dengan menggunakan komputer IBM (Bah. II)
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Cover image for Introduction to VLSI testing
91. 
Cover image for Programmable digital feature telephone; Pengawalan kelajuan motor aruhan menggunakan elektronik kuasa; Microcomputer based controller design for robot arm system; Analog line card (1); Pengujian I.C. digital dengan menggunakan komputer IBM (Bah. II); Pengawal berasaskan komputer untuk Hampden H MRS 1; Perolehan dan pemprosesan data sistem mengajar bermodul menggunakan mikrokomputer ed controller design for robot arm system;
92. 
Cover image for Geometri sungai Kelang dalam keadaan regim; Pengujian I.C TTL dan CMOS menggunakan IBM PC; Jelmaan fast fourier : suatu kaedah pemprosesan bayangan digit; Penggunaan keluk pembelajaran dalam pemindahan teknologi di projek pembinaan UTM; Sekudai, Johor; Peningkatan taraf produktiviti di dalam kerja-kerja penyenggaraan lokomotif di Keretapi Tanah Melayu = pruductivity improvement in the maintenance of locomotives in Keretapi Tanah Melayu; Short circuit fault level analysis; Protocol study on IBM PC partial implementation of X.25; In circuit digital I.C tester;
93. 
Cover image for Developments in integrated circuit testing
94. 
Cover image for LSI/VLSI testability design
95. 
Cover image for VLSI testing
96. 
Cover image for VLSI design of a data test set; Kajian pecahtebat dalam gas SF6 (sulfur heksafluroid); Assembly line tracking ability of robot; Proses control using computer; Design of control circuit for batik printer; Keupayaan minyak kelapa sawit sebagai minyak penebat
97. 
Cover image for VLSI : testing & validation techniques
98. 
Cover image for Proceedings of reliability physics
99. 
Cover image for Proceedings of reliability physics
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Cover image for Proceedings of reliability physics
101. 
Cover image for Compatibility and testing of electronic components
102. 
Cover image for 68000-based digital circuit troubleshooting system in-circuit and board-level testing
103. 
Cover image for Harmonized system of quality assessment for electronic components : generic specification : film and hybrid integrated circuits
104. 
Cover image for In-circuit digital I.C. tester
105. 
Cover image for Integrated electronic circuits and micro-assemblies of assessed quality : generic data and methods of test
106. 
Cover image for High-speed DTL digital gate and associated extender circuits of assessed quality. General application category
107. 
Cover image for DTL digital gate circuits of assessed quality. General application category
108. 
Cover image for High-speed DTL inverter circuits of assessed quality. General application category
109. 
Cover image for Custom-built integrated circuits of assessed quality : generic data and methods of test
110. 
Cover image for Testing analogue circuits by power supply voltage control testing technique : an analysis at bias point
111. 
Cover image for Memory LSI, linear IC : digest of papers
112. 
Cover image for Memory & LSI : digest of papers
113. 
Cover image for Design for in-situ chip testing with a compact tester
114. 
Cover image for In-circuit testing may shorten life of ICs
115. 
Cover image for MC6800 based programmable digital integrated circuit tester