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Fakulti Kejuruteraan Elektrik
(99)
Razali Ismail, supervisor
(23)
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Tan, Michael Loong Peng, supervisor
(5)
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Metal oxide semiconductors, Complementary
(130)
Metal oxide semiconductors
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1. 
Cover image for Temperature dependence of the resistivity for metal-oxide semiconductors based on tin dioxide
2. 
Cover image for Temperature dependence of the resistivity for metal-oxide semiconductors based on tin oxide
3. 
Cover image for Oxides and oxide films
4. 
Cover image for CMOS : Circuit Design, Layout, and Simulation
5. 
Cover image for Effect of Germanium content on mobility enhancement of strained silicon fet
6. 
Cover image for Effect of Germanium content on mobility enhancement of strained silicon fet
7. 
Cover image for Gate-all-around floating-gate (GAA-FG) with variable oxide thickness for nonvolatile memory
8. 
Cover image for Gate-all-around floating-gate (GAA-FG) with variable oxide thickness for nonvolatile memory
9. 
Cover image for A high speed photon counting design in a standard 0.13μm complementary metal oxide semiconductor process
10. 
Cover image for A high speed photon counting design in a standard 0.13μm complementary metal oxide semiconductor process
11. 
Cover image for Optimization of N-channel silicon nanowire field effect transistor using Taguchi method
12. 
Cover image for Optimization of N-channel silicon nanowire field effect transistor using Taguchi method
13. 
Cover image for The Future of Semiconductor oxides in Next-Generation Solar Cells
14. 
Cover image for Performance evaluation of 3-d n-chanel and p-channel twin silicon nanowire mosfet (TSNWFET)
15. 
Cover image for Performance evaluation of 3-d n-chanel and p-channel twin silicon nanowire mosfet (TSNWFET)
16. 
Cover image for Performance evaluation of 22NM FinFET based 6-T SRAM cell
17. 
Cover image for Performance evaluation of 22NM FinFET based 6-T SRAM cell
18. 
Cover image for Complementary metal oxide semiconductor electrocardiogram amplifier for low power wearable cardiac screening
19. 
Cover image for Complementary metal oxide semiconductor electrocardiogram amplifier for low power wearable cardiac screening
20. 
Cover image for Optical tomographic system based on complementary metal oxide semiconductor area image sensor
21. 
Cover image for Optical tomographic system based on complementary metal oxide semiconductor area image sensor
22. 
Cover image for CMOS and beyond : logic switches for terascale integrated circuits
23. 
Cover image for CMOS digital integrated circuits : analysis and design
24. 
Cover image for CMOS : front-end electronics for radiation sensors
25. 
Cover image for Physical and chemical characterization of oxide/germanium interfaces in ge mosfet
26. 
Cover image for Metal oxide surge arrester trending and analysis
27. 
Cover image for Metal oxide surge arrester trending and analysis
28. 
Cover image for Growth and characterization of zinc oxide nanostructures on graphene by electrochemical deposition technique
29. 
Cover image for Physical and chemical characterization of oxide/germanium interfaces in ge mosfet
30. 
Cover image for Analog filters in nanometer CMOS
31. 
Cover image for The MOS system
32. 
Cover image for Fully integrated impedimetric deoxyribonucleic acid biosensor design using 0.18 um complementary metal oxide semiconductor technology
33. 
Cover image for Design of low power 900MHz complementary metal oxide semiconductor voltage controlled oscillator for 0.25 µm process
34. 
Cover image for Design of low power 900MHz complementary metal oxide semiconductor voltage controlled oscillator for 0.25 µm process
35. 
Cover image for Testing for small-delay defects in nanoscale CMOS integrated circuits
36. 
Cover image for Beyond-CMOS nanodevices
37. 
Cover image for Structural electronic and magnetic properties of diluted magnetic semiconductors based on transition metals doped zinc oxide
38. 
Cover image for Channel length effects on the characteristic of submicron nLDD-mosfet exposed to gamma radiation
39. 
Cover image for Design and implementation of A 1-bit finfet full adder cell in subthreshold region
40. 
Cover image for Design and implementation of A 1-bit finfet full adder cell in subthreshold region
41. 
Cover image for Channel length effects on the characteristic of submicron nLDD-mosfet exposed to gamma radiation
42. 
Cover image for Structural, electronic and magnetic properties of diluted magnetic semiconductors based on transition metals doped zinc oxide
43. 
Cover image for Fully integrated impedimetric deoxyribonucleic acid biosensor design using 0.18 um complementary metal oxide semiconductor technology
44. 
Cover image for Strain-engineered MOSFETs
45. 
Cover image for Technology computer aided design : simulation for VLSI MOSFET
46. 
Cover image for Modeling and performance evaluation of graphene based field effect transistor
47. 
Cover image for Compensation technique using CMOS active inductor
48. 
Cover image for CMOS sigma-delta converters : practical design guide
49. 
Cover image for Analog IC reliability in nanometer CMOS
50. 
Cover image for Fundamentals of nanoscaled field effect transistors
51. 
Cover image for Bio/CMOS interfaces and co-design
52. 
Cover image for Quantum mechanical effects on the performance of strained silicon metal-oxide-semiconductor field-effect transistor
53. 
Cover image for Quantum mechanical effects on the performance of strained silicon metal-oxide-semiconductor field-effect transistor
54. 
Cover image for Design of CMOS operational amplifiers
55. 
Cover image for Compensation technique using CMOS active inductor
56. 
Cover image for Device and circuit-level performance of graphene nanoribbon field-effect transistor with benchmarking against a nano-mosfet
57. 
Cover image for Device and circuit-level performance of graphene nanoribbon field-effect transistor with benchmarking against a nano-mosfet
58. 
Cover image for CMOS nanoelectronics : innovative devices, architectures, and applications
59. 
Cover image for Fundamentals of ultra-thin-body MOSFETs and FinFETs
60. 
Cover image for Design of the optical tomography system for four projections CMOS linear image sensor
61. 
Cover image for Modelling and simulation of nanoscale non-planar double gate metal-oxide-semiconductor field effect transistor
62. 
Cover image for Modelling and simulation of nanoscale non-planar double gate metal-oxide-semiconductor field effect transist
63. 
Cover image for Graphene nanoribbon based CMOS modelling
64. 
Cover image for Graphene nanoribbon based CMOS modelling
65. 
Cover image for Nano-CMOS gate dielectric engineering
66. 
Cover image for Micro CMOS design
67. 
Cover image for CMOS analog circuit design
68. 
Cover image for Transparent conducting oxides and applications : symposium held November 29-December 3 [2010], Boston, Massachusetts, U.S.A.
69. 
Cover image for Simulation and modeling of curved channel metal oxide semiconductor field effect transisto
70. 
Cover image for Surge arrester condition monitoring using leakage current and thermography techniques
71. 
Cover image for Surge arrester condition monitoring using leakage current and thermography techniques
72. 
Cover image for Simulation and modeling of curved channel metal oxide semiconductor field effect transistor
73. 
Cover image for Simulation and analysis on the effects of multiple faults in CMOS analogue circuit
74. 
Cover image for Simulation and analysis on the effects of multiple faults in CMOS analogue circuit
75. 
Cover image for Modelling of MEMS Fabry Perot pressure sensor using CMOS fabrication process
76. 
Cover image for Design of the optical tomography system for four projections CMOS linear image sensor
77. 
Cover image for Advanced circuits for emerging technologies
78. 
Cover image for Engineering the CMOS library : enhancing digital design kits for competitive silicon
79. 
Cover image for Integrated 60GHz RF beamforming in CMOS
80. 
Cover image for CMOS circuits for passive wireless microsystems
81. 
Cover image for Design analog cells based on threshold voltage reduction technique
82. 
Cover image for CMOS analog integrated circuits : high speed and power efficient design
83. 
Cover image for The chemistry of nanostructured materials
84. 
Cover image for Design analog cells based on threshold voltage reduction technique
85. 
Cover image for Design of nanoscale vertical impact ionization metal oxide semiconductor field effect transistor (MOSFET) for short channel effect control
86. 
Cover image for CMOS VLSI design : a circuits and systems perspective
87. 
Cover image for Integrated circuit design
88. 
Cover image for Nanoscale MOS transistors : semi-classical transport and applications
89. 
Cover image for Design of nanoscale vertical impact ionization metal oxide semiconductor field effect transistor (MOSFET) for short channel effect control
90. 
Cover image for Characterization of tri-material gate n-channel MOSFET
91. 
Cover image for Characterization of tri-material gate n-channel MOSFET
92. 
Cover image for Development of labview based driver for CMOS linear image sensor
93. 
Cover image for The influence of corner effects in double gate vertical mosfet
94. 
Cover image for Measurements of metal-oxide surge arresters leakage currents by using MOSAIMS
95. 
Cover image for Measurements of metal-oxide surge arresters leakage currents by using MOSAIMS
96. 
Cover image for Development of partially and fully depleted silicon-on-insulator MOSFET using tcad tools
97. 
Cover image for Design and analysis of double gate vertical MOSFET (VMOSFET) comparison between source on top and drain on top
98. 
Cover image for CMOS analog design using all-region MOSFET modeling
99. 
Cover image for CMOS : circuit design, layout, and simulation
100. 
Cover image for Thin film metal-oxides : fundamentals and applications in electronics and energy
101. 
Cover image for Materials and devices for end-of-roadmap and beyond CMOS scaling : symposium held April 5-9, 2010, San Francisco, California
102. 
Cover image for Nanoscale CMOS VLSI circuits : design for manufacturability
103. 
Cover image for The influence of corner effects in double gate vertical mosfet
104. 
Cover image for Design and characterisation of biaxial strained silicon N-channel MOSFET
105. 
Cover image for Design and characterisation of biaxial strained silicon N-channel MOSFET
106. 
Cover image for Design and analysis of double gate vertical MOSFET (VMOSFET) comparison between source on top and drain on top
107. 
Cover image for Two-dimensional analytical threshold voltage model of nanoscale strained silicon MOSFET with tri-material gate
108. 
Cover image for Design of complementary metal -oxide - semiconductor radio frequency modules with active inductor using standard complementary metal -oxide- semiconductor process
109. 
Cover image for Vertical channel structure and ballistic carrier transport of nanoscale metal oxide semiconductor field effect transistor
110. 
Cover image for The development of vertical mosfet model incorporating a dielectric pocket
111. 
Cover image for Design of complementary metal -oxide - semiconductor radio frequency modules with active inductor using standard complementary metal -oxide- semiconductor process
112. 
Cover image for Vertical channel structure and ballistic carrier transport of nanoscale metal oxide semiconductor field effect transistorh[electronic resource]
113. 
Cover image for Physics and operation of silicon devices in integrated circuits
114. 
Cover image for Modeling of electrical, process and temperature variations in metal-oxide-semiconductor transistor mismatch
115. 
Cover image for Modeling of electrical, process and temperature variations in metal-oxide-semiconductor transistor mismatch
116. 
Cover image for Reliability wearout mechanisms in advanced CMOS technologies
117. 
Cover image for CMOS analog circuit design
118. 
Cover image for Fundamentals of modern VLSI devices
119. 
Cover image for Design and characterization of nanoscale metal -oxide- semiconductor field effect transistor incorporating dielectric pocket
120. 
Cover image for Design for testability for complementary metal oxide semiconductor analog circuit to detect parametric variation of gate leakage
121. 
Cover image for Mobility enhancement of nanoscale biaxial strained silicon metal-oxide semiconductor field effect transistor
122. 
Cover image for Multiple lightning effects on electrical characteristics forward current and forward voltage of a combination mov-opto as low voltage protective device
123. 
Cover image for Multiple lightning effects on electrical characteristics forward current and forward voltage of a combination mov-opto as low voltage protective device
124. 
Cover image for Characterization of punchthrough effects in vertical mosfet incorporating a dielectric pocket
125. 
Cover image for Electrodeposition of metal oxide semiconductor photocatalysts on support for degradation of benzene-toluene-xylene in aqueous system
126. 
Cover image for Performance and evaluation of carbon nanotube based transistor and circuit
127. 
Cover image for The development of vertical mosfet model incorporating a dielectric pocket
128. 
Cover image for CMOS : mixed-signal circuit design
129. 
Cover image for Compact MOSFET models for VLSI design
130. 
Cover image for Defects in microelectronic materials and devices
131. 
Cover image for Mobility enhancement of nanoscale biaxial strained silicon metal-oxide semiconductor field effect transistor
132. 
Cover image for Design methodology for RF CMOS phase locked loops
133. 
Cover image for Transient-induced latchup in CMOS integrated circuits
134. 
Cover image for Design and characterization of nanoscale metal -oxide- semiconductor field effect transistor incorporating dielectric pocket
135. 
Cover image for Design for testability for complementary metal oxide semiconductor analog circuit to detect parametric variation of gate leakage
136. 
Cover image for Silicon devices and process integration
137. 
Cover image for Electronic device architectures for the nano-CMOS era : from ultimate CMOS scaling to beyond CMOS devices
138. 
Cover image for CMOS circuit design, layout, and simulation
139. 
Cover image for Velocity field characteristics in quasi-two-dimensional (q2d) systems: application to nano-mosfet
140. 
Cover image for Modeling of lightly of doped drain (LDD) mosfet for circuit simulation
141. 
Cover image for Semi-empirical device models for nano-mosfet
142. 
Cover image for Characterization and model development of complementary metal oxide semiconductor floating gate defect
143. 
Cover image for Simulation of device fabrication and parameter extraction for circuit performance evaluation
144. 
Cover image for Characterization of double gate silicon on insulator (SOI) MOSFET
145. 
Cover image for Semi - empirical capacitance modeling for mosfet
146. 
Cover image for Wireless technologies : circuits, systems and devices
147. 
Cover image for CMOS active inductors and transformers : principle, implementation, and applications
148. 
Cover image for CMOS SRAM circuit design and parametric test in nano-scaled technologies : process-aware sram design and test
149. 
Cover image for Design and modeling of millimeter-wave CMOS circuits for wireless transceivers : era of sub-100nm technology
150. 
Cover image for Nanometer CMOS ICs : from basics to ASICs
151. 
Cover image for Design of high voltage xDSL line drivers in standard CMOS
152. 
Cover image for Low power UWB CMOS radar sensors
153. 
Cover image for Nano-CMOS design for manufacturability : robust circuit and physical design for sub-65nm technology nodes
154. 
Cover image for Fabrication of SiGe HBT BiCMOS technology
155. 
Cover image for Low-power high-level synthesis for nanoscale CMOS circuits
156. 
Cover image for Photodegradation of cobalt amine and binuclear ferum complexes by using metal oxide semiconductor (TiO2, ZnO, WO3, and Al2O3) as catalysts
157. 
Cover image for Characterization and model development of complementary metal oxide semiconductor floating gate defect
158. 
Cover image for The physics and modeling of MOSFETs : surface-potential model HiSIM
159. 
Cover image for Structured analog CMOS design
160. 
Cover image for CMOS current-mode circuits for data communications
161. 
Cover image for Current-voltage characteristics and model for short-chanel MOSFET
162. 
Cover image for Design and characterisation of strained silicon MOSFET
163. 
Cover image for Defect-oriented testing for nano-metric CMOS VLSI circuits
164. 
Cover image for Vlsi implementation of down conversion mixer for CMOS RF transceiver
165. 
Cover image for Characterization of binary decision diagram (BDD) based single - electron basic logic circuit by using simon
166. 
Cover image for VLSI implementation of power amplifier for CMOS RF transceiver
167. 
Cover image for Semi - empirical modeling of carbon nanotube field - effect trasistor (CNFET)
168. 
Cover image for Modeling of deep submicron silicon on insulator (SOI) mosfet
169. 
Cover image for Optimization of device performance using semiconductor TCAD tools
170. 
Cover image for Semi - empirical device model for nanoscale MOSFET
171. 
Cover image for Characterization of silicon - on - insulator (SOI) mosfet using TCAD tools
172. 
Cover image for Advanced fabrication techniques for designing nanoscale mosfet
173. 
Cover image for Characterization of low power delay product MOSFET-like CNFET
174. 
Cover image for A complementary metal oxide semiconductor low noise amplifier using integrated active inductor
175. 
Cover image for Advanced CMOS cell design
176. 
Cover image for Basics of CMOS cell design
177. 
Cover image for Modeling and simulation of drain induced barrier lowering in short channel metal oxide semiconductor field effect transistor
178. 
Cover image for CMOS biotechnology
179. 
Cover image for Characterization of high transonductance mosfet-like carbon nanotube field effect transistor
180. 
Cover image for Modeling of lightly doped drain (LDD) MOSFET for ciruit simulation
181. 
Cover image for Power management of digital circuits in deep sub-micron CMOS technologies
182. 
Cover image for Optimization of nanoscale complementary metal oxide semiconductor performance
183. 
Cover image for Broadband Opto-Electrical Receivers in Standard CMOS
184. 
Cover image for A complementary metal oxide semiconductor low noise amplifier using integrated active inductor
185. 
Cover image for Vlsi implementation of down conversion mixer for CMOS RF transceiver
186. 
Cover image for Modeling of lightly doped drain (LDD) MOSFET for ciruit simulation
187. 
Cover image for Optimization of device performance using semiconductor TCAD tools
188. 
Cover image for Characterization of silicon - on - insulator (SOI) mosfet using TCAD tools
189. 
Cover image for Optimization of manoscale complementary metal oxide semiconductor performance
190. 
Cover image for Modeling and simulation of drain induced barrier lowering in short channel metal oxide semiconductor field effect transistor
191. 
Cover image for Semi - empirical device model for nanoscale MOSFET
192. 
Cover image for Characterization of binary decision diagram (BDD) based single - electron basic logic circuit by using simon
193. 
Cover image for VLSI implementation of power amplifier for CMOS RF transceiver
194. 
Cover image for Semi - empirical modeling of carbon nanotube field - effect trasistor (CNFET)
195. 
Cover image for Modeling of deep submicron silicon on insulator (SOI) mosfet
196. 
Cover image for Advanced fabrication techniques for designing nanoscale mosfet
197. 
Cover image for Characterization of low power delay product MOSFET-like CNFET
198. 
Cover image for Current-voltage characteristics and model for short-chanel MOSFET
199. 
Cover image for Design and characterisation of strained silicon MOSFET
200. 
Cover image for CMOS/CCD sensors and camera systems
201. 
Cover image for Analysis of bipolar and CMOS amplifiers
202. 
Cover image for Microlithography : science and technology
203. 
Cover image for New insights on ballistic versus scattering-limited transport in a nanoscale metal-oxide-semiconductor-field-effect-transistor
204. 
Cover image for Tradeoffs and optimization in analog CMOS design
205. 
Cover image for Mosfet modeling for circuit analysis and design
206. 
Cover image for Mosfet modeling for VLSI simulation : theory and practice
207. 
Cover image for Hybrid CMOS single-electron-transistor device and circuit design
208. 
Cover image for Charge-based MOS transistor modeling : the EKV model for low-power and RF IC design
209. 
Cover image for Multiple supply and threshold voltage CMOS circuits
210. 
Cover image for Transistor level modeling for analog/ RF IC design
211. 
Cover image for Nanoscale transistors : device physics, modeling and simulation
212. 
Cover image for Kesan dedenyut berbilang kilat ekor panjang (Long - tailed) terhadap ciri - ciri elektrik metal oxide varistor (MOV)
213. 
Cover image for Surge protective device for hybrid system and MOV degradation indicator
214. 
Cover image for Kesan dedenyut berbilang kilat ekor panjang (LONG - TAILED) terhadap ciri - ciri, kearuhan (L) dan kemuatan (C) bagi Metal Oqide Varistor (MOV)
215. 
Cover image for Low-power CMOS circuits : technology, logic design and CAD tools
216. 
Cover image for All-digital frequency synthesizer in deep-submicron CMOS
217. 
Cover image for Hybrid CMOS single-electron-transistor device and circuit design
218. 
Cover image for Chip design for submicron VLSI : CMOS layout and simulation
219. 
Cover image for Penentuan voltan dan arus lebihan dari MOV berasaskan model elektrikl
220. 
Cover image for A study on metal oxide varistor voltage-current characteristics under heavy current stresses
221. 
Cover image for Chip design for submicron VLSI CMOS layout and simulation
222. 
Cover image for Power semiconductors
223. 
Cover image for Leakage in nanometer CMOS technologies
224. 
Cover image for CMOS cascade sigma-delta modulators for sensors and telecom : error analysis and practical design
225. 
Cover image for Design and implement a DC drive using a half bridge DC-DC converter
226. 
Cover image for Modeling and simulation of deep submicron mosfet
227. 
Cover image for Voltage reference CMOS bandgap
228. 
Cover image for The design of 900MHZ ring - VCO (Voltage Controller Oscillator) using 0. 25um CMOS technology
229. 
Cover image for Demystifying chipmaking
230. 
Cover image for Simulation of 0.18 micron mosfet and its characterization
231. 
Cover image for Demystifying chipmaking
232. 
Cover image for CMOS VLSI design : a circuits and systems perspective
233. 
Cover image for Nano-CMOS circuit and physical design
234. 
Cover image for CMOS-MEMS
235. 
Cover image for Simulation of 0.18 micron MOSFET and its characterization
236. 
Cover image for CMOS PLL synthesizers : analysis and design
237. 
Cover image for LNA-ESD co-design for fully integrated CMOS wireless receivers
238. 
Cover image for Matching properties of deep sub-micron MOS transistors
239. 
Cover image for 24 channels analogue input acquisition recorder for annealing furnace
240. 
Cover image for Simulation of CMOS fabrication process using silvaco software
241. 
Cover image for Sistem ampaian automatik
242. 
Cover image for Perbandingan ciri - ciri elektrik metal oxide varistor (MOV) dengan gas discharge tube (GDT) sebagai peranti perlindungan pusuan
243. 
Cover image for Integrated CMOS circuits for optical communications
244. 
Cover image for Low-power deep sub-micron CMOS logic : sub-threshold current reduction
245. 
Cover image for CMOS electronics : how it works, how it fails
246. 
Cover image for Digitally assisted pipeline ADCs : theory and implementation
247. 
Cover image for Static crosstalk-noise analysis : for deep sub-micron digital designs
248. 
Cover image for CMOS imagers : from phototransduction to image processing
249. 
Cover image for CMOS PLLs and VCOs for 4G wireless
250. 
Cover image for Simulation of CMOS fabrication process using silvaco software
251. 
Cover image for Sistem ampaian automatik
252. 
Cover image for Perbandingan ciri - ciri elektrik metal oxide varistor (MOV) dengan gas discharge tube (GDT) sebagai peranti perlindungan pusuan
253. 
Cover image for The design of CMOS radio-frequency integrated circuits
254. 
Cover image for Low cost PLC (Program Logic Control)
255. 
Cover image for Pemodelan metal oxide varistor (MOV) menggunakan simulasi PSpice berdasarkan ciri-ciri fizikal
256. 
Cover image for Menganggarkan rating pemain catur
257. 
Cover image for MOS (metal oxide semiconductor) physics and technology
258. 
Cover image for Low-power CMOS design for wireless transceivers
259. 
Cover image for Design of low-voltage CMOS switched-opamp switched-capacitor systems
260. 
Cover image for Multi-threshold CMOS digital circuits : managing leakage power
261. 
Cover image for CMOS digital integrated circuits : analysis and design
262. 
Cover image for Kesan dedenyut kilat terhadap MOV (metal oxide varistor) dengan simulasi Matlab
263. 
Cover image for CMOS integrated analog-to-digital and digital-to-analog converters
264. 
Cover image for Device modeling for analog and RF CMOS circuit design
265. 
Cover image for Design of high-performance cmos voltage-controlled oscillators
266. 
Cover image for VLSI design of CMOS correlator
267. 
Cover image for Kajian mengenai sistem perlindungan kilat dan kesan kerosakan struktur tempat awam akibat panahan kilat
268. 
Cover image for Process and device simulation for MOSFET fabrication using virtual wafer fab-athena and atlas software
269. 
Cover image for Process and device simulation for MOSFET fabrication using virtual wafer fab-athena and atlas software
270. 
Cover image for CMOS : mixed-signal circuit design
271. 
Cover image for Smart power ICs : technologies and applications
272. 
Cover image for CMOS/BiCMOS ULSI : low voltage, low power
273. 
Cover image for CMOS VLSI designs of transmitter and receiver in the Universal Synchronous Receiver/Transmitter (USRT)
274. 
Cover image for Mendiagnosis kecacatan suatu litar bentangan penambah penuh CMOS
275. 
Cover image for Parameter extraction and geometry effect on the electronical properties of submicron mos transistors
276. 
Cover image for Systematic design for optimisation of pipelined ADCs
277. 
Cover image for Design of analog CMOS integrated circuits
278. 
Cover image for Parameter extraction and geometry effect on the electronical properties of submicron MOS transistors
279. 
Cover image for Membina litar pendarab menggunakan teknologi BICMOS
280. 
Cover image for Cmos cell-library for mosis scn process part IV
281. 
Cover image for Silicon VLSI technology : fundamentals, practice and modeling
282. 
Cover image for Cmos cell library for mosis scn process part v
283. 
Cover image for Pemodelan Metal Oxide Varistor berdasarkan kepada ciri-ciri fizikal
284. 
Cover image for Faktor kegagalan bagi metal oxide varistor (MOV) sebagai peranti perlindungan terhadap dedenyut kilat
285. 
Cover image for Pembangunan cell library menggunakan proses CMOS MOSIS bahagian VI
286. 
Cover image for Cell library development for mosis scalable cmos process, part III
287. 
Cover image for CMOS cell-library for mosis scn process part II
288. 
Cover image for Cmos cell library for mosis scn process part I
289. 
Cover image for Electrothermal analysis of VLSI systems
290. 
Cover image for Cell library development for mosis scalable cmos process, part III
291. 
Cover image for Operation and modeling of the MOS transistor
292. 
Cover image for Effect of temperature and methane on the electrical conductivity of SnO2 (100-x) Pd(x) semiconductor gas sensor systems
293. 
Cover image for Caracterisation de structures mos submicroniques et analyse de defauts induits par irradiation gamma : extrapolation aux defauts induits dans les oxydes transistors bipolaires
294. 
Cover image for Motion detection in stereoscopic vision system
295. 
Cover image for Fuzzy logic based reactive navigation behaviours for walking and wall climbing robot
296. 
Cover image for Sensors, cameras, and systems for scientific/industrial applications
297. 
Cover image for Analysis on layout dependent defects of CMOS digital circuit
298. 
Cover image for IC design of a CMOS battery charger
299. 
Cover image for The digital IC gallery
300. 
Cover image for Introduction to CMOS OP-AMPs and comparators
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