Crystal growth and evaluation of silicon for VLSI and ULSI

Silicon, as a single-crystal semiconductor, has sparked a revolution in the field of electronics and touched nearly every field of science and technology. Though available abundantly as silica and in various other forms in nature, silicon is difficult to separate from its chemical compounds because of its reactivity. As a solid, silicon is chemically inert and stable, but growing it as a single crystal creates many technological challenges.

Crystal Growth and Evaluation of Silicon for VLSI and ULSI is one of the first books to cover the systematic growth of silicon single crystals and the complete evaluation of silicon, from sand to useful wafers for device fabrication. Written for engineers and researchers working in semiconductor fabrication industries, this practical text:

Describes different techniques used to grow silicon single crystals Explains how grown single-crystal ingots become a complete silicon wafer for integrated-circuit fabrication Reviews different methods to evaluate silicon wafers to determine suitability for device applications Analyzes silicon wafers in terms of resistivity and impurity concentration mapping Examines the effect of intentional and unintentional impurities Explores the defects found in regular silicon-crystal lattice Discusses silicon wafer preparation for VLSI and ULSI processing

Crystal Growth and Evaluation of Silicon for VLSI and ULSI is an essential reference for different approaches to the selection of the basic silicon-containing compound, separation of silicon as metallurgical-grade pure silicon, subsequent purification, single-crystal growth, and defects and evaluation of the deviations within the grown crystals.

Author Notes

Golla Eranna obtained his master's degree from Sri Venkateswara University, Tirupati, India, with a top rank in the field of semiconductor physics. After that, he joined and received his Ph.D from the Indian Institute of Technology (IIT) Madras. Later, he moved to the IIT Kharagpur Microelectronics Centre. Dr. Eranna joined CEERI, Pilani, India, as a scientist and is currently a senior principal scientist. He became a professor under the Academy of Scientific and Innovative Research (CSIR, New Delhi), and regularly lectures on VLSI processing technology. He also maintains a full-fledged semiconductor device fabrication laboratory.

Preface	p. xiii
About the Author	p. xvii
1 Introduction	p. 1
1.1 Silicon: The Semiconductor	p. 2
1.2 Why Single Crystals	p. 2
1.3 Revolution in Integrated Circuit Fabrication Technology and the; Art of Device Miniaturization	p. 4
1.4 Use of Silicon as a Semiconductor	p. 6
1.5 Silicon Devices for Boolean Applications	p. 11
1.6 Integration of Silicon Devices and the Art of Circuit Miniaturization	p. 12
1.7 MOS and CMOS Devices for Digital Applications	p. 18
1.8 LSI, VLSI, and ULSI Circuits and Applications	p. 18
1.9 Silicon for MEMS Applications	p. 20
1.10 Summary	p. 23
References	p. 23
2 Silicon: The Key Material for Integrated Circuit Fabrication Technology	p. 27
2.1 Introduction	p. 27
2.2 Preparation of Raw Silicon Material	p. 28
2.3 Metallurgical-Grade Silicon	p. 29
2.4 Purification of Metallurgical-Grade Silicon	p. 31
2.5 Ultra-High Pure Silicon for Electronics Applications	p. 37
2.6 Poly crystalline Silicon Feed for Crystal Growth	p. 37
2.7 Summary	p. 41
References	p. 41
3 Importance of Single Crystals for Integrated Circuit Fabrication	p. 45
3.1 Introduction	p. 45
3.2 Crystal Structures	p. 45
3.2.1 Different Crystal Structures in Nature	p. 47
3.2.2 Cubic Structures	p. 47
3.3 Diamond Crystal Structure	p. 47
3.3.1 Silicon Crystal Structure	p. 47
3.3.2 Silicon Crystals and Atomic Packing Factors	p. 48
3.4 Crystal Order and Perfection	p. 48
3.5 Crystal Orientations and Planes	p. 50
3.6 Influence of Dopants and Impurities in Silicon Crystals	p. 54
3.7 Summary	p. 58
References	p. 58
4 Different Techniques for Growing Single-Crystal Silicon	p. 59
4.1 Introduction	p. 59
4.2 Bridgman Crystal Growth Technique	p. 60
4.3 Czochralski Crystal Growth/Pulling Technique	p. 60
4.3.1 Crucible Choice for Molten Silicon	p. 64
4.3.2 Chamber Temperature Profile	p. 72
4.3.3 Seed Selection for Crystal Pulling	p. 77
4.3.4 Environmental and Ambient Control in the Crystal Chamber	p. 82
4.3.5 Crystal Pull Rate and Seed/Crucible Rotation	p. 84
4.3.6 Dopant Addition for Growing Doped Crystals	p. 94
4.3.6.1 Boron	p. 94
4.3.6.2 Phosphorus	p. 95
4.3.6.3 Arsenic	p. 96
4.3.6.4 Gallium	p. 96
4.3.6.5 Nitrogen	p. 96
4.3.6.6 Antimony	p. 97
4.3.6.7 Germanium	p. 99
4.3.7 Methods for Continuous Czochralski Crystal Growth	p. 100
4.3.8 Impurity Segregation Between Liquid and Grown Silicon Crystals	p. 102
4.3.9 Crystal Growth Striations	p. 107
4.3.10 Use of a Magnetic Field in the Czochralski Growth Technique	p. 108
4.3.11 Large-Area Silicon Crystals for VLSI and ULSI Applications	p. 117
4.3.12 Post-Growth Thermal Gradient and Crystal Cooling after Pull-Out	p. 122
4.4 Float-Zone Crystal Growth Technique	p. 124
4.4.1 Seed Selection	p. 125
4.4.2 Environment and Chamber Ambient Control	p. 125
4.4.3 Heating Mechanisms and RF Coil Shape	p. 125
4.4.4 Crystal Growth Rate and Seed Rotation	p. 126
4.4.5 Dopant Distribution in Growing Crystals	p. 128
4.4.6 Impurity Segregation between Liquid and Grown Silicon Crystals	p. 130
4.4.7 Use of Magnetic Fields for Float-Zone Growth	p. 130
4.4.8 Large Area Silicon Crystals and Limitations of Shape and Size	p. 131
4.4.9 Thermal Gradient and Post-Growth Crystal Cooling	p. 135
4.5 Zone Refining of Single-Crystal Silicon	p. 135
4.6 Other Silicon Crystalline Structures and Growth Techniques	p. 136
4.6.1 Silicon Ribbons	p. 136
4.6.2 Silicon Sheets	p. 137
4.6.3 Silicon Whiskers and Fibers	p. 137
4.6.4 Silicon in Circular and Spherical Shapes	p. 137
4.6.5 Silicon Hollow Tubes	p. 138
4.6.6 Casting of Polycrystalline Silicon for Photovoltaic Applications	p. 138
4.7 Summary	p. 138
References	p. 139
5 From Silicon Ingots to Silicon Wafers	p. 157
5.1 Introduction	p. 157
5.2 Radial Resistivity Measurements	p. 157
5.3 Boule Formation, Identification of Crystal Orientation, and Flats	p. 158
5.4 Ingot Slicing	p. 162
5.5 Mechanical Lapping of Wafer Slices	p. 164
5.6 Edge Profiling of Slices	p. 167
5.7 Chemical Etching and Mechanical Damage Removal	p. 167
5.8 Chemimechanical Polishing for Planar Wafers	p. 168
5.9 Surface Roughness and Overall Wafer Topography	p. 170
5.10 Megasonic Cleaning	p. 170
5.11 Final Cleaning and Inspection	p. 171
5.12 Summary	p. 171
References	p. 172
6 Evaluation of Silicon Wafers	p. 175
6.1 Introduction	p. 175
6.2 Acoustic Laser Probing Technique	p. 175
6.3 Atomic-Force Microscope Studies on Surfaces	p. 178
6.4 Auger Electron Spectroscopic Studies	p. 178
6.5 Chemical Staining and Etching Techniques	p. 181
6.6 Contactless Characterization	p. 184
6.7 Deep-Level Transient Spectroscopy	p. 185
6.8 Defect Decoration by Metals	p. 187
6.9 Electron Beam and High-Energy Electron Diffraction Studies	p. 188
6.10 Flame Emission Spectrometry	p. 188
6.11 Four-Point Probe Technique for Resistivity Measurement and Mapping	p. 189
6.12 Fourier Transform Infrared Spectroscopy Measurements for Impurity Identification	p. 191
6.13 Gas Fusion Analysis	p. 195
6.14 Hall Mobility	p. 195
6.15 Mass Spectra Analysis	p. 196
6.16 Minority Carrier Diffusion Length/Lifetime/Surface Photovoltage	p. 197
6.17 Optical Methods for Impurity Evaluation	p. 199
6.18 Photoluminescence Method for Determining Impurity Concentrations	p. 199
6.19 Gamma-Ray Diffractometry	p. 201
6.20 Scanning Electron Microscopy for Defect Analysis	p. 201
6.21 Scanning Optical Microscope	p. 202
6.22 Secondary Ion Mass Spectrometer for Impurity Distribution	p. 203
6.23 Spreading Resistance and Two-Point Probe Measurement Technique	p. 205
6.24 Stress Mea surements	p. 207
6.25 Transmission Electron Microscopy	p. 209
6.26 van der Pauw Resistivity Measurement Technique for Irregular-Shaped Wafers	p. 210
6.27 X-ray Technique for Crystal Perfection and Dislocation Density	p. 210
6.28 Summary	p. 214
References	p. 214
7 Resistivity and Impurity Concentration Mapping of Silicon Wafers	p. 225
7.1 Introduction	p. 225
7.2 Electrically Active and Inactive Impurities	p. 228
7.3 Surface Mapping and Concentration Contours	p. 228
7.4 Surface Roughness Mapping on a Complete Wafer	p. 229
7.5 Summary	p. 244
References	p. 245
8 Impurities in Silicon Wafers	p. 247
8.1 Effect of Intentional and Unintentional Impurities and Their Influence on Silicon Devices	p. 247
8.2 Intentional Dopant Impurities in Silicon Wafers	p. 250
8.2.1 Aluminum	p. 250
8.2.2 Antimony	p. 250
8.2.3 Arsenic	p. 251
8.2.4 Boron	p. 252
8.2.5 Gallium	p. 253
8.2.6 Phosphorus	p. 253
5.3 Unintentional Dopant Impurities in Silicon Wafers	p. 254
8.3.1 Carbon	p. 255
8.3.2 Chromium	p. 259
8.3.3 Copper	p. 260
8.3.4 Germanium	p. 261
8.3.5 Gold	p. 261
8.3.6 Helium	p. 262
8.3.7 Hydrogen	p. 262
8.3.8 Iron	p. 263
8.3.9 Nickel	p. 265
8.310 Nitrogen	p. 265
8.3.11 Oxygen	p. 268
8.3.12 Tin	p. 281
8.4 Other Metallic Impurities	p. 282
8.5 Summary	p. 282
References	p. 283
9 Defects in Silicon Wafers	p. 293
9.1 Introduction	p. 293
9.2 Impact of Defects in Silicon Devices and Structures	p. 294
9.3 Point Defects and Vacancies	p. 298
9.4 Line Defects	p. 304
9.5 Bulk Defects and Voids	p. 306
9.6 Dislocations and Screw Dislocations	p. 310
9.7 Swirl Defects	p. 312
9.8 Stacking Faults	p. 315
9.9 Precipitations	p. 322
9.10 Surface Pits/Crystal-Originated Particles	p. 326
9.11 Grown Vacancies and Defects	p. 329
9.12 Thermal Donors	p. 331
9.13 Slips, Cracks, and Shape Irregularities	p. 332
9.14 Stress, Bowing, and Warpage	p. 334
9.15 Summary	p. 337
References	p. 337
10 Silicon Wafer Preparation for VLSI and ULSI Processing	p. 347
10.1 Introduction	p. 347
10.2 Purity of Chemicals Used for Silicon Processing	p. 347
10.3 Degreasing of Silicon Wafers	p. 348
10.4 Removal of Metallic and Other Impurities	p. 348
10.5 Gettering of Metallic Impurities	p. 351
10.6 Denuding of Silicon Wafers	p. 362
10.7 Neutron Irradiation	p. 366
10.8 Argon Annealing of Wafers	p. 366
10.9 Hydrogen Annealing of Wafers	p. 368
10.10 Final Cleaning, Rinsing, and Wafer Drying	p. 371
10.11 Summary	p. 371
References	p. 372
11 Packing of Silicon Wafers	p. 377
11.1 Tacking of Fully Processed Blank Silicon Wafers	p. 377
11.2 Storage of Wafers and Control of Particulate Contamination	p. 388
11.3 Storage of Wafers and Control of Particulate Contamination with Process-Bound Wafers	p. 392
11.4 Summary	p. 392
References	p. 393
Index	p. 395

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