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Summary
Summary
This text/reference provides students and practicing engineers with an introduction to the classical methods of designing electrical circuits, but incorporates modern logic design techniques used in the latest microprocessors, microcontrollers, microcomputers, and various LSI components. The book provides a review of the classical methods e.g., the basic concepts of Boolean algebra, combinational logic and sequential logic procedures, before engaging in the practical design approach and the use of computer-aided tools. The book is enriched with numerous examples (and their solutions), over 500 illustrations, and includes a CD-ROM with simulations, additional figures, and third party software to illustrate the concepts discussed in the book.
Author Notes
Arijit Saha is an instructor of electronics and communication engineering at JIS College of Engineering
Nilotpal Manna is a senior faculty member in electronics engineering at JIS College of Engineering
Table of Contents
Preface | p. xiii |
1 Data and Number Systems | p. 1 |
1.1 Introduction | p. 1 |
1.2 Number Systems | p. 2 |
1.3 Conversion between Number Systems | p. 2 |
1.4 Complements | p. 10 |
1.5 Binary Arithmetic | p. 13 |
1.6 1's And 2's Complement Arithmetic | p. 17 |
1.7 Signed Binary Numbers | p. 19 |
1.8 7's And 8's Complement Arithmetic | p. 21 |
1.9 9's And 10's Complement Arithmetic | p. 23 |
1.10 15's And 16's Complement Arithmetic | p. 25 |
1.11 BCD Addition | p. 27 |
1.12 BCD Subtraction | p. 28 |
Review Questions | p. 30 |
2 Codes and Their Conversions | p. 31 |
2.1 Introduction | p. 31 |
2.2 Codes | p. 31 |
2.3 Solved Problems | p. 44 |
Review Questions | p. 49 |
3 Boolean Algebra and Logic Gates | p. 51 |
3.1 Introduction | p. 51 |
3.2 Basic Definitions | p. 51 |
3.3 Definition of Boolean Algebra | p. 52 |
3.4 Two-valued Boolean Algebra | p. 54 |
3.5 Basic Properties And Theorems of Boolean Algebra | p. 55 |
3.6 Venn Diagram | p. 57 |
3.7 Boolean Functions | p. 58 |
3.8 Simplification of Boolean Expressions | p. 59 |
3.9 Canonical And Standard Forms | p. 60 |
3.10 Other Logic Operators | p. 67 |
3.11 Digital Logic Gates | p. 67 |
3.12 Positive And Negative Logic | p. 83 |
3.13 Concluding Remarks | p. 84 |
Review Questions | p. 85 |
4 Simplification and Minimization of Boolean Functions | p. 89 |
4.1 Introduction | p. 89 |
4.2 Two-variable Karnaugh Maps | p. 89 |
4.3 Three-variable Karnaugh Maps | p. 90 |
4.4 Four-variable Karnaugh Maps | p. 93 |
4.5 Five-variable Karnaugh Maps | p. 99 |
4.6 Six-variable Karnaugh Maps | p. 100 |
4.7 Don't-care Combinations | p. 102 |
4.8 The Tabulation Method | p. 103 |
4.9 More Examples | p. 106 |
4.10 Variable-entered Karnaugh Maps | p. 113 |
4.11 Concluding Remarks | p. 123 |
Review Questions | p. 123 |
5 Combinational Logic Circuits | p. 125 |
5.1 Introduction | p. 125 |
5.2 Design Procedure | p. 126 |
5.3 Adders | p. 126 |
5.4 Subtractors | p. 129 |
5.5 Code Conversion | p. 132 |
5.6 Parity Generator And Checker | p. 141 |
5.7 Some Examples of Combinational Logic Circuits | p. 143 |
5.8 Combinational Logic with MSI And LSI | p. 156 |
5.9 Four-bit Binary Parallel Adder | p. 157 |
5.10 Magnitude Comparator | p. 167 |
5.11 Decoders | p. 168 |
5.12 Encoders | p. 174 |
5.13 Multiplexers or Data Selectors | p. 175 |
5.14 Demultiplexers or Data Distributors | p. 188 |
5.15 Concluding Remarks | p. 190 |
Review Questions | p. 190 |
6 Programmable Logic Devices | p. 193 |
6.1 Introduction | p. 193 |
6.2 PLD Notation | p. 195 |
6.3 Read Only Memory (ROM) | p. 195 |
6.4 Programmable Logic Array (PLA) | p. 202 |
6.5 Programmable Array Logic (PAL) Devices | p. 208 |
6.6 Registered PAL Devices | p. 210 |
6.7 Configurable PAL Devices | p. 211 |
6.8 Generic Array Logic Devices | p. 211 |
6.9 Field-Programmable Gate Array (FPGA) | p. 211 |
6.10 Concluding Remarks | p. 212 |
Review Questions | p. 212 |
7 Sequential Logic Circuits | p. 215 |
7.1 Introduction | p. 215 |
7.2 Flip-flops | p. 216 |
7.3 Types of Flip-flops | p. 218 |
7.4 Clocked S-R Flip-flop | p. 221 |
7.5 Clocked D Flip-flop | p. 225 |
7.6 J-K Flip-flop | p. 228 |
7.7 T Flip-flop | p. 233 |
7.8 Toggling Mode of S-R and D Flip-flops | p. 235 |
7.9 Triggering of Flip-flops | p. 235 |
7.10 Excitation Table of a Flip-flop | p. 237 |
7.11 Interconversion of Flip-flops | p. 237 |
7.12 Sequential Circuit Model | p. 248 |
7.13 Classification of Sequential Circuits | p. 248 |
7.14 Analysis of Sequential Circuits | p. 250 |
7.15 Design Procedure of Sequential Circuits | p. 254 |
Review Questions | p. 260 |
8 Registers | p. 263 |
8.1 Introduction | p. 263 |
8.2 Shift Register | p. 263 |
8.3 Serial-in-Serial-out Shift Register | p. 264 |
8.4 Serial-in-Parallel-out Register | p. 269 |
8.5 Parallel-in-Serial-out Register | p. 270 |
8.6 Parallel-in-Parallel-out Register | p. 272 |
8.7 Universal Register | p. 274 |
8.8 Shift Register Counters | p. 276 |
8.9 Sequence Generator | p. 279 |
8.10 Serial Addition | p. 283 |
8.11 Binary Divider | p. 284 |
Review Questions | p. 289 |
9 Counters | p. 291 |
9.1 Introduction | p. 291 |
9.2 Asynchronous (Serial or Ripple) Counters | p. 292 |
9.3 Asynchronous Counter ICs | p. 302 |
9.4 Synchronous (Parallel) Counters | p. 309 |
9.5 Synchronous Down-Counter | p. 311 |
9.6 Synchronous Up-Down Counter | p. 312 |
9.7 Design Procedure of Synchronous Counter | p. 313 |
9.8 Synchronous/Asynchronous Counter | p. 325 |
9.9 Presettable Counter | p. 326 |
9.10 Synchronous Counter ICs | p. 327 |
9.11 Counter Applications | p. 335 |
9.12 Hazards in Digital Circuits | p. 338 |
Review Questions | p. 344 |
10 A/D and D/A Conversion | p. 345 |
10.1 Introduction | p. 345 |
10.2 Digital-to-Analog Converters (DAC) | p. 345 |
10.3 Specification of D/A Converters | p. 355 |
10.4 An Example of a D/A Converter | p. 357 |
10.5 Analog-to-Digital Converters | p. 360 |
10.6 Specification of an A/D Converter | p. 371 |
10.7 An Example of an A/D Converter IC | p. 372 |
10.8 Concluding Remarks | p. 374 |
Review Questions | p. 374 |
11 Logic Family | p. 377 |
11.1 Introduction | p. 377 |
11.2 Characteristics of Digital IC | p. 379 |
11.3 Bipolar Transistor Characteristics | p. 382 |
11.4 Resistor-Transistor Logic (RTL) | p. 385 |
11.5 Diode Transistor Logic (DTL) | p. 387 |
11.6 Transistor Transistor Logic (TTL) | p. 389 |
11.7 Emitter-Coupled Logic (ECL) | p. 407 |
11.8 Integrated-Injection Logic (I[subscript 2]L) | p. 410 |
11.9 Metal Oxide Semiconductor (MOS) | p. 412 |
11.10 Comparison of Different Logic Families | p. 420 |
11.11 Interfacing | p. 421 |
11.12 Some Examples | p. 424 |
Review Questions | p. 427 |
Appendix 1 Alternate Gate Symbols | p. 431 |
Appendix 2 74 Series Integrated Circuits | p. 433 |
Appendix 3 Pin Configuration of 74 Series Integrated Circuits | p. 439 |
Appendix 4 4000 Series Integrated Circuits | p. 459 |
Appendix 5 Pin Configuration of 4000 Series Integrated Circuits | p. 465 |
Appendix 6 About the CD-ROM | p. 481 |
Glossary | p. 483 |
Bibliography | p. 487 |
Index | p. 489 |