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Code design for dependable systems : theory and practical applications
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New York,NY : John Wiley & Sons, 2006


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30000010113083 QA268 F84 2006 Open Access Book

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Theoretical and practical tools to master matrix code designstrategy and technique

Error correcting and detecting codes are essential to improvingsystem reliability and have popularly been applied to computersystems and communication systems. Coding theory has been studiedmainly using the code generator polynomials; hence, the codes aresometimes called polynomial codes. On the other hand, the codesdesigned by parity check matrices are referred to in this book asmatrix codes. This timely book focuses on the design theory formatrix codes and their practical applications for the improvementof system reliability. As the author effectively demonstrates,matrix codes are far more flexible than polynomial codes, as theyare capable of expressing various types of code functions.

In contrast to other coding theory publications, this one does notburden its readers with unnecessary polynomial algebra, but ratherfocuses on the essentials needed to understand and take fulladvantage of matrix code constructions and designs. Readers arepresented with a full array of theoretical and practical tools tomaster the fine points of matrix code design strategy andtechnique:
* Code designs are presented in relation to practical applications,such as high-speed semiconductor memories, mass memories of disksand tapes, logic circuits and systems, data entry systems, anddistributed storage systems
* New classes of matrix codes, such as error locating codes, spottybyte error control codes, and unequal error control codes, areintroduced along with their applications
* A new parallel decoding algorithm of the burst error controlcodes is demonstrated

In addition to the treatment of matrix codes, the author providesreaders with a general overview of the latest developments andadvances in the field of code design. Examples, figures, andexercises are fully provided in each chapter to illustrate conceptsand engage the reader in designing actual code and solving realproblems. The matrix codes presented with practical parametersettings will be very useful for practicing engineers andresearchers. References lead to additional material so readers canexplore advanced topics in depth.

Engineers, researchers, and designers involved in dependable systemdesign and code design research will find the unique focus andperspective of this practical guide and reference helpful infinding solutions to many key industry problems. It also can serveas a coursebook for graduate and advanced undergraduate students.

Author Notes

Eiji Fujiwara, PhD, is Professor at the Tokyo Institute of Technology

Table of Contents

Prefacep. ix
1 Introductionp. 3
1.1 Faults and Failuresp. 3
1.2 Error Modelsp. 6
1.3 Error Recovery Techniques for Dependable Systemsp. 10
1.4 Code Design Process for Dependable Systemsp. 16
Referencesp. 19
2 Mathematical Background and Matrix Codesp. 23
2.1 Introduction to Algebrap. 23
2.2 Linear Codesp. 33
2.3 Basic Matrix Codesp. 48
Exercisesp. 71
Referencesp. 75
3 Code Design Techniques for Matrix Codesp. 77
3.1 Minimum-Weight & Equal-Weight-Row Codesp. 78
3.2 Odd-Weight-Column Codesp. 82
3.3 Even-Weight-Row Codesp. 84
3.4 Odd-Weight-Row Codesp. 86
3.5 Rotational Codesp. 87
Exercisesp. 92
Referencesp. 93
4 Codes for High-Speed Memories I: Bit Error Control Codesp. 97
4.1 Modified Hamming SEC-DED Codesp. 98
4.2 Modified Double-Bit Error Correcting BCH Codesp. 105
4.3 On-Chip ECCsp. 110
Exercisesp. 123
Referencesp. 126
5 Codes for High-Speed Memories II: Byte Error Control Codesp. 133
5.1 Single-Byte Error Correcting (SbEC) Codesp. 134
5.2 Single-Byte Error Correcting and Double-Byte Error Detecting (SbEC-DbED) Codesp. 154
5.3 Single-Byte Error Correcting and Single p-Byte within a Block Error Detecting (SbEC-S[subscript pxb/B]ED) Codesp. 171
Exercisesp. 180
Referencesp. 183
6 Codes for High-Speed Memories III: Bit/Byte Error Control Codesp. 187
6.1 Single-Byte / Burst Error Detecting SEC-DED Codesp. 188
6.2 Single-Byte Error Correcting and Double-Bit Error Detecting (SbEC-DED) Codesp. 217
6.3 Single-Byte Error Correcting and Double-Bit Error Correcting (SbEC-DEC) Codesp. 230
6.4 Single-Byte Error Correcting and Single-Byte Plus Single-Bit Error Detecting (SbEC-(Sb + S)ED) Codesp. 244
Exercisesp. 254
Referencesp. 258
7 Codes for High-Speed Memories IV: Spotty Byte Error Control Codesp. 263
7.1 Spotty Byte Errorsp. 264
7.2 Single Spotty Byte Error Correcting (S[subscript t/b]EC) Codesp. 264
7.3 Single Spotty Byte Error Correcting and Single-Byte Error Detecting (S[subscript t/b]EC-SbED) Codesp. 274
7.4 Single Spotty Byte Error Correcting and Double Spotty Byte Error Detecting (S[subscript t/b]EC-D[subscript t/b]ED) Codesp. 284
7.5 A General Class of Spotty Byte Error Control Codesp. 290
Exercisesp. 326
Referencesp. 330
8 Parallel Decoding Burst / Byte Error Control Codesp. 335
8.1 Parallel Decoding Burst Error Control Codesp. 336
8.2 Parallel Decoding Cyclic Burst Error Correcting Codesp. 351
8.3 Transient Behavior of Parallel Encoder / Decoder Circuits of Error Control Codesp. 353
Exercisesp. 369
Referencesp. 370
9 Codes for Error Location: Error Locating Codesp. 373
9.1 Error Location of Faulty Packages and Faulty Chipsp. 373
9.2 Block Error Locating (S[subscript b/pxb]EL) Codesp. 376
9.3 Single-Bit Error Correcting and Single-Block Error Locating (SEC-S[subscript b/pxb]EL) Codesp. 377
9.4 Single-Bit Error Correcting and Single-Byte Error Locating (SEC-S[subscript e/b]EL) Codesp. 389
9.5 Burst Error Locating Codesp. 396
9.6 Code Conditions for Error Locating Codesp. 404
Exercisesp. 409
Referencesp. 410
10 Codes for Unequal Error Control/Protection (UEC / UEP)p. 413
10.1 Error Models for UEC Codes and UEP Codesp. 413
10.2 Fixed-Byte Error Control UEC Codesp. 417
10.3 Burst Error Control UEC / UEP Codesp. 427
10.4 Application of the UEC / UEP Codesp. 439
Exercisesp. 457
Referencesp. 461
11 Codes for Mass Memoriesp. 465
11.1 Tape Memory Codesp. 465
11.2 Magnetic Disk Memory Codesp. 487
11.3 Optical Disk Memory Codesp. 500
Exercisesp. 509
Referencesp. 512
12 Coding for Logic and System Designp. 517
12.1 Self-checking Conceptp. 518
12.2 Self-testing Checkersp. 536
12.3 Self-checking ALUp. 552
12.4 Self-checking Design for Computer Systemsp. 570
Exercisesp. 585
Referencesp. 590
13 Codes for Data Entry Systemsp. 599
13.1 M-Ary Asymmetric Errors in Data Entry Systemsp. 599
13.2 M-Ary Asymmetric Symbol Error Correcting Codesp. 600
13.3 Nonsystematic M-Ary Asymmetric Error Correcting Codes with Deletion / Insertion / Adjacent-Symbol-Transposition Error Correction Capabilitiesp. 623
13.4 Codes for Two-Dimensional Matrix Symbolsp. 632
Exercisesp. 644
Referencesp. 646
14 Codes for Multiple / Distributed Storage Systemsp. 649
14.1 MDS Array Codes Tolerating Multiple-Disk Failuresp. 650
14.2 Codes for Distributed Storage Systemsp. 661
Exercisesp. 675
Referencesp. 677
Indexp. 679