Register transfer level design of compression processor core using verilog hardware description language

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Title:

Register transfer level design of compression processor core using verilog hardware description language

Personal Author:

Roslee Mohd. Sabri, 1978-

Publication Information:

Skudai : Universiti Teknologi Malaysia, 2007

Physical Description:

xvi, 181 p. : ill. ; 30 cm. + 1 CD-ROM (12 cm.)

General Note:

Also available in CD-ROM : CP 015017 ra

Supervisor : Prof. Dr. Mohamed Khalil Mohd Hani

Subject Term:

Data compression (Telecommunication)

Added Author:

Mohamed Khalil Mohd Hani, supervisor

Added Corporate Author:

Fakulti Kejuruteraan Elektrik

DSP_DISSERTATION:

Thesis (Sarjana Kejuruteraan (Elektrik - Elektronik dan Telekomunikasi)) -Universiti Teknologi Malaysia, 2007

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... FKE Library	FKE30000005406	TK5102.5 R674 2007	Closed Access Thesis	UTM Master Thesis (Closed Access)	Searching... Unknown
Searching... Perpustakaan Raja Zarith Sofiah	30000010153855	TK5102.5 R674 2007	Closed Access Thesis	UTM Master Thesis (Closed Access)	Searching... Unknown

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