Introduction to logic design

Title:

Personal Author:

Marcovitz, Alan B.

Edition:

3rd ed.

Publication Information:

New York, NY : McGraw-Hill Science, 2010

Physical Description:

xii, 637 p. : ill. ; 24 cm.

ISBN:

9780073191645

Subject Term:

Logic circuits

Logic design

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010201553	TK7868.L6 M37 2010	Open Access Book	Book	Searching... Unknown

Introduction to Logic Design by Alan Marcovitz is intended for the first course in logic design, taken by computer science, computer engineering, and electrical engineering students. As with the previous editions, this edition has a clear presentation of fundamentals and an exceptional collection of examples, solved problems and exercises.

The text integrates laboratory experiences, both hardware and computer simulation, while not making them mandatory for following the main flow of the chapters. Design is emphasized throughout, and switching algebra is developed as a tool for analyzing and implementing digital systems. The presentation includes excellent coverage of minimization of combinational circuits, including multiple output ones, using the Karnaugh map and iterated consensus. There are a number of examples of the design of larger systems, both combinational and sequential, using medium scale integrated circuits and programmable logic devices.

The third edition features two chapters on sequential systems. The first chapter covers analysis of sequential systems and the second covers design. Complete coverage of the analysis and design of synchronous sequential systems adds to the comprehensive nature of the text. The derivation of state tables from word problems further emphasizes the practical implementation of the material being presented.

Preface	p. ix
Chapter 1 Introduction	p. 1
1.1 Logic Design	p. 1
1.1.1 The Laboratory	p. 3
1.2 A Brief Review of Number Systems	p. 4
1.2.1 Hexadecimal	p. 8
1.2.2 Binary Addition	p. 9
1.2.3 Signed Numbers	p. 11
1.2.4 Binary Subtraction	p. 14
1.2.5 Binary Coded Decimal (BCD)	p. 16
1.2.6 Other Codes	p. 17
1.3 Solved Problems	p. 19
1.4 Exercises	p. 25
1.5 Chapter 1 Test	p. 27
Chapter 2 Combinational Systems	p. 29
2.1 The Design Process for Combinational Systems	p. 29
2.1.1 Don't Care Conditions	p. 32
2.1.2 The Development of Truth Tables	p. 33
2.2 Switching Algebra	p. 37
2.2.1 Definition of Switching Algebra	p. 38
2.2.2 Basic Properties of Switching Algebra	p. 40
2.2.3 Manipulation of Algebraic Functions	p. 43
2.3 Implementation of Functions with AND, OR, and NOT Gates	p. 48
2.4 The Complement	p. 52
2.5 From the Truth Table to Algebraic Expressions	p. 54
2.6 NAND, NOR, and Exclusive-OR Gates	p. 59
2.7 Simplification of Algebraic Expressions	p. 65
2.8 Manipulation of Algebraic Functions and NAND Gate Implementations	p. 70
2.9 A More General Boolean Algebra	p. 78
2.10 Solved Problems	p. 80
2.11 Exercises	p. 100
2.12 Chapter 2 Test	p. 108
Chapter 3 The Karnaugh Map	p. 111
3.1 Introduction to the Karnaugh Map	p. 111
3.2 Minimum Sum of Product Expressions Using the Karnaugh Map	p. 121
3.3 Don't Cares	p. 135
3.4 Product of Sums	p. 140
3.5 Five- and Six-Variable Maps	p. 143
3.6 Multiple Output Problems	p. 150
3.7 Solved Problems	p. 162
3.8 Exercises	p. 191
3.9 Chapter 3 Test	p. 196
Chapter 4 Function Minimization Algorithms	p. 201
4.1 Quine-McCluskey Method for One Output	p. 201
4.2 Iterated Consensus for One Output	p. 204
4.3 Prime Implicant Tables for One Output	p. 208
4.4 Quine-McCluskey for Multiple Output Problems	p. 216
4.5 Iterated Consensus for Multiple Output Problems	p. 219
4.6 Prime Implicant Tables for Multiple Output Problems	p. 222
4.7 Solved Problems	p. 226
4.8 Exercises	p. 246
4.9 Chapter 4 Test	p. 247
Chapter 5 Designing Combinational Systems	p. 249
5.1 Iterative Systems	p. 250
5.1.1 Delay in Combinational Logic Circuits	p. 250
5.1.2 Adders	p. 252
5.1.3 Subtractors and Adder/Subtractors	p. 256
5.1.4 Comparators	p. 256
5.2 Binary Decoders	p. 258
5.3 Encoders and Priority Encoders	p. 268
5.4 Multiplexers and Demultiplexers	p. 269
5.5 Three-State Gates	p. 274
5.6 Gate Arrays-ROMs, PLAs, and PALs	p. 276
5.6.1 Designing with Read-Only Memories	p. 280
5.6.2 Designing with Programmable Logic Arrays	p. 281
5.6.3 Designing with Programmable Array Logic	p. 284
5.7 Testing and Simulation of Combinational Systems	p. 289
5.7.1 An Introduction to Verilog	p. 289
5.8 Larger Examples	p. 292
5.8.1 A One-Digit Decimal Adder	p. 292
5.8.2 A Driver for a Seven-Segment Display	p. 293
5.8.3 An Error Coding System	p. 301
5.9 Solved Problems	p. 305
5.10 Exercises	p. 348
5.11 Chapter 5 Test	p. 360
Chapter 6 Analysis of Sequential Systems	p. 365
6.1 State Tables and Diagrams	p. 366
6.2 Latches	p. 370
6.3 Flip Flops	p. 371
6.4 Analysis of Sequential Systems	p. 380
6.5 Solved Problems	p. 390
6.6 Exercises	p. 403
6.7 Chapter 6 Test	p. 412
Chapter 7 The Design of Sequential Systems	p. 415
7.1 Flip Flop Design Techniques	p. 420
7.2 The Design of Synchronous Counters	p. 437
7.3 Design of Asynchronous Counters	p. 447
7.4 Derivation of State Tables and State Diagrams	p. 450
7.5 Solved Problems	p. 465
7.6 Exercises	p. 483
7.7 Chapter 7 Test	p. 491
Chapter 8 Solving Larger Sequential Problems	p. 493
8.1 Shift Registers	p. 493
8.2 Counters	p. 499
8.3 Programmable Logic Devices (PLDs)	p. 506
8.4 Design Using ASM Diagrams	p. 511
8.5 One-Hot Encoding	p. 515
8.6 Verilog for Sequential Systems	p. 516
8.7 Design of a Very Simple Computer	p. 518
8.8 Other Complex Examples	p. 520
8.9 Solved Problems	p. 527
8.10 Exercises	p. 537
8.11 Chapter 8 Test	p. 541
Chapter 9 Simplification of Sequential Circuits
View Chapter 9 at http://www.mhhe.com/marcovitz
9.1 A Tabular Method for State Reduction	p. 3
9.2 Partitions	p. 10
9.2.1 Properties of Partitions	p. 13
9.2.2 Finding SP Partitions	p. 14
9.3 State Reduction using Partitions	p. 17
9.4 Choosing a State Assignment	p. 22
9.5 Solved Problems	p. 28
9.6 Exercises	p. 44
9.7 Chapter 9 Test	p. 48
Appendix A Relating the Algebra to the Karnaugh Map	p. 543
Appendix B Answers to Selected Exercises	p. 548
Appendix C Chapter Test Answers	p. 573
Appendix D Laboratory Experiments	p. 587
D.1 Hardware Logic Lab	p. 587
D.2 WinBreadboard™ and MacBreadboardTM	p. 591
D.3 Introduction to LogicWorks	p. 593
D.4 A Set of Logic Design Experiments	p. 598
D.4.1 Experiments Based on Chapter 2 Material	p. 598
D.4.2 Experiments Based on Chapter 5 Material	p. 600
D.4.3 Experiments Based on Chapter 6 Material	p. 603
D.4.4 Experiments Based on Chapter 7 Material	p. 605
D.4.5 Experiments Based on Chapter 8 Material	p. 606
D.5 Layout of Chips Referenced in the Text and Experiments	p. 607
Appendix E Complete Examples	p. 612
Index	p. 629

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