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Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
|---|---|---|---|---|---|
Searching... | 30000010059975 | TK7887.6 M87 2004 | Open Access Book | Book | Searching... |
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Summary
Summary
Digitally Assisted Pipeline ADCs: Theory and Implementation explores the opportunity to reduce ADC power dissipation by leveraging digital signal processing capabilities in fine line integrated circuit technology. The described digitally assisted pipelined ADC uses a statistics-based system identification technique as an enabling element to replace precision residue amplifiers with simple open-loop gain stages. The digital compensation of analog circuit distortion eliminates one key factor in the classical noise-speed-linearity constraint loop and thereby enables a significant power reduction.
Digitally Assisted Pipeline ADCs: Theory and Implementation describes in detail the implementation and measurement results of a 12-bit, 75-MSample/sec proof-of-concept prototype. The Experimental converter achieves power savings greater than 60% over conventional implementations.
Digitally Assisted Pipeline ADCs: Theory and Implementationwill be of interest to researchers and professionals interested in advances of state-of-the-art in A/D conversion techniques.
Table of Contents
| List of Figures |
| List of Tables |
| Acknowledgements |
| Preface |
| 1 Introduction |
| 1 Motivation |
| 2 Overview |
| 3 Chapter Organization |
| 2 Performance Trends |
| 1 Introduction |
| 2 Digital Performance Trends |
| 3 ADC Performance Trends |
| 3 Scaling Analysis |
| 1 Introduction |
| 2 Basic Device Scaling from a Digital Perspective |
| 3 Technology Metrics for Analog Circuits |
| 4 Scaling Impact on Matching-Limited Circuits |
| 5 Scaling Impact on Noise-Limited Circuits |
| 4 Improving Analog Circuit Efficiency |
| 1 Introduction |
| 2 Analog Circuit Challenges |
| 3 The Cost of Feedback |
| 4 Two-Stage Feedback Amplifier vs. Open-Loop Gain Stage |
| 5 Discussion |
| 5 Open-Loop Pipelined ADCs |
| 1 A Brief Review of Pipelined ADCs |
| 2 Conventional Stage Implementation |
| 3 Open-Loop Pipeline Stages |
| 4 Alternative Transconductor Implementations |
| 6 Digital Nonlinearity Correction |
| 1 Overview |
| 2 Error Model and Digital Correction |
| 3 Alternative Error Models |
| 7 Statistics-Based Parameter Estimation |
| 1 Introduction |
| 2 Modulation Approach |
| 3 Required Sub-ADC and Sub-DAC Redundancy |
| 4 Parameter Estimation Based on Residue Differences |
| 5 Statistics Based Difference Estimation |
| 6 Complete Estimation Block |
| 7 Simulation Example |
| 8 Discussion |
| 8 Prototype Implementation |
| 1 ADC Architecture |
| 2 Stage 1 |
| 3 Stage 2 |
| 4 Post-Processor |
| 9 Experimental Results |
| 1 Layout and Packaging |
| 2 Test Setup |
| 3 Measured Results |
| 4 Post-Processor Complexity |
| 10 Conclusion |
| 1 Summary |
| 2 Suggestions for Future Work |
| Appendices |
| A Open-Loop Charge Redistribution |
| B |
| C |
| 1 Time Constant |
| 2 Output Variance |
| 3 Maximum Gain Parameters |
| References |
| Index |
