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Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
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Searching... | 30000004859264 | QA76.9.C62 P37 2000 | Open Access Book | Book | Searching... |
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Summary
Summary
Ideal for graduate and senior undergraduate level courses in computer arithmetic and advanced digital design, Computer Arithmetic: Algorithms and Hardware Designs provides a balanced, comprehensive treatment of computer arithmetic, covering topics in arithmetic unit design and circuit implementation that complement the architectural and algorithmic speedup techniques used in high-performance computer architecture and parallel processing. Using a unified and consistent framework, the text begins with number representation and proceeds through basic arithmetic operations, floating-point arithmetic, and function evaluation methods. Later chapters cover broad design and implementation topics--including techniques for high-throughput, low-power, and fault-tolerant arithmetic--and also feature brief case studies. An indispensable resource for instruction, professional development, and research in digital computer arithmetic, Computer Arithmetic: Algorithms and Hardware Designs combines broad coverage of the underlying theories of computer arithmetic with numerous examples of practical designs, worked-out examples, and a large collection of meaningful problems. Features: · Divided into 28 lecture-size chapters · Emphasizes both the underlying theories of computer arithmetic and actual hardware designs · Carefully links computer arithmetic to other subfields of computer engineering · Includes over 450 end-of-chapter problems ranging in complexity from simple exercises to mini-projects · Incorporates many examples of practical designs · Uses consistent standardized notation throughout · Instructor's manual includes solutions to text problems, additional exercises, test questions, and enlarged versions of figures and charts
Author Notes
BehroozParhamiProfessor in the Department of Electrical and Computer EngineeringUniversity of California, Santa Barbara.
Table of Contents
Preface |
Part I Number Representation |
1 Numbers and Arithmetic |
1.1 What is Computer Arithmetic? |
1.2 A Motivating Example |
1.3 Numbers and Their Encodings |
1.4 Fixed-Radix Positional Number Systems |
1.5 Number Radix Conversion |
1.6 Classes of Number Representations |
2 Representing Signed Numbers |
2.1 Signed-Magnitude Representation |
2.2 Biased Representations |
2.3 Complement Representations |
2.4 Two's- and 1's-Complement Numbers |
2.5 Direct and Indirect Signed Arithmetic |
2.6 Using Signed Positions or Signed Digits |
3 Redundant Number Systems |
3.1 Coping with the Carry Problem |
3.2 Redundancy in Computer Arithmetic |
3.3 Digit Sets and Digit-Set Conversions |
3.4 Generalized Signed-Digit Numbers |
3.5 Carry-Free Addition Algorithms |
3.6 Conversions and Support Functions |
4 Residue Number Systems |
4.1 RNS Representation and Arithmetic |
4.2 Choosing the RNS Moduli |
4.3 Encoding and Decoding of Numbers |
4.4 Difficult RNS Arithmetic Operations |
4.5 Redundant RNS Representations |
4.6 Limits of Fast Arithmetic in RNS |
Part II Addition/Subtraction |
5 Basic Addition and Counting |
5.1 Bit-Serial and Ripple-Carry Adders |
5.2 Conditions and Exceptions |
5.3 Analysis of Carry Propagation |
5.4 Carry Completion Detection |
5.5 Addition of a Constant: Counters |
5.6 Manchester Carry Chains and Adders |
6 Carry-Lookahead Adders |
6.1 Unrolling the Carry Recurrence |
6.2 Carry-Lookahead Adder Design |
6.3 Ling Adder and Related Designs |
6.4 Carry Determination as Prefix Computation |
6.5 Alternative Parallel Prefix Networks |
6.6 VLSI Implementation Aspects |
7 Variations in Fast Adders |
7.1 Simple Carry-Skip Adders |
7.2 Multilevel Carry-Skip Adders |
7.3 Carry-Select Adders |
7.4 Conditional-Sum Adder |
7.5 Hybrid Adder Designs |
7.6 Optimizations in Fast Adders |
8 Multi-Operand Addition |
8.1 Using Two-Operand Adders |
8.2 Carry-Save Adders |
8.3 Wallace and Dadda Trees |
8.4 Parallel Counters |
8.5 Generalized Parallel Counters |
8.6 Adding Multiple Signed Numbers |
Part III Multiplication |
9 Basic Multiplication Schemes |
9.1 Shift/Add Multiplication Algorithms |
9.2 Programmed Multiplication |
9.3 Basic Hardware Multipliers |
9.4 Multiplication of Signed Numbers |
9.5 Multiplication by Constants |
9.6 Preview of Fast Multipliers |
10 High-Radix Multipliers |
10.1 Radix-4 Multiplication |
10.2 Modified Booth's Recoding |
10.3 Using Carry-Save Adders |
10.4 Radix-8 and Radix-16 Multipliers |
10.5 Multibeat Multipliers |
10.6 VLSI Complexity Issues |
11 Tree and Array Multipliers |
11.1 Full Tree Multipliers |
11.2 Alternative Reduction Trees |
11.3 Tree Multipliers for Signed Numbers |
11.4 Partial-Tree Multipliers |
11.5 Array Multipliers |
11.6 Pipelined Tree and Array Multipliers |
12 Variations in Multipliers |
12.1 Divide-and-Conquer Designs |
12.2 Additive Multiply Modules |
12.3 Bit-Serial Multipliers |
12.4 Modular Multipliers |
12.5 The Special Case of Squaring |
12.6 Combined Multiply-Add Units |
Part IV Division |
13 Basic Divis |