Digital design and computer organization

Digital Design and Computer Organization introduces digital design as it applies to the creation of computer systems. It summarizes the tools of logic design and their mathematical basis, along with in depth coverage of combinational and sequential circuits.

The book includes an accompanying CD that includes the majority of circuits highlighted in the text, delivering you hands-on experience in the simulation and observation of circuit functionality. These circuits were designed and tested with a user-friendly Electronics Workbench package (Multisim Textbook Edition) that enables your progression from truth tables onward to more complex designs.

This volume differs from traditional digital design texts by providing a complete design of an AC-based CPU, allowing you to apply digital design directly to computer architecture. The book makes minimal reference to electrical properties and is vendor independent, allowing emphasis on the general design principles.

Reviews 1

Choice Review

Farhat (Univ. of Nebraska, Omaha) offers a book on digital design and computer organization that treats these topics in a somewhat traditional manner, from a computer engineering/electronic engineering perspective. He emphasizes digital design and approaches computer organization from a digital design perspective. As such, the book has a strong upper-level undergraduate focus in digital design. It is not for the casual reader, but readers with a strong software background may find this book an excellent way to expand their knowledge and see the relationships between their software background and experience and the field of digital design. There are eleven chapters; variations of the first nine chapters, as described in the preface, may be used in a typical three-credit course. There is an exercise section at the end of each chapter and excellent figures and graphics throughout. The book contains a brief but complete set of references and an outstanding collection of completed exercises in an appendix. ^BSumming Up: Recommended. Upper-division undergraduates through professionals. J. Beidler University of Scranton

1 Numbers in Different Bases	p. 1
1.1 Digital and Analog Data	p. 2
1.2 Coding	p. 2
1.3 Positional Number System	p. 3
1.3.1 Numbers without Radix Point	p. 4
1.3.2 Numbers with Radix Point	p. 5
1.4 Octal and Hexadecimal Bases	p. 6
1.5 Operands Types and Their Range	p. 8
1.5.1 Data Types	p. 9
1.5.2 Finite Range	p. 9
1.6 Conversion of Decimal Numbers to Equivalent Numbers in Arbitrary Bases	p. 11
1.6.1 Conversion of Integer Part	p. 11
1.6.2 Converting the Fractional Part	p. 13
1.7 Binary Arithmetic	p. 15
1.7.1 Addition	p. 15
1.7.2 Subtraction	p. 17
1.7.3 Multiplication	p. 19
1.8 Radix and Diminished Radix Complements	p. 20
1.9 Representation of Negative Numbers	p. 22
1.9.1 The Three Representations	p. 23
1.9.2 Range of the Numbers	p. 24
1.10 Coding and Binary Codes	p. 25
1.10.1 BCD Code	p. 26
1.10.2 The Excess-m Code	p. 27
1.10.3 Gray Code	p. 28
1.10.4 Character Codes	p. 29
1.11 Floating-Point Numbers	p. 30
1.11.1 Binary Representation of Floating-Point	p. 30
1.11.2 Normalized and Biased Floating-Point Representation	p. 32
Chapter 1 Exercises	p. 35
2 Boolean Algebra, and Gate and Transistor Design	p. 37
2.1 Boolean or Switching Algebra	p. 38
2.1.1 Definitions	p. 38
2.1.2 Boolean Expressions	p. 39
2.1.3 Truth Tables	p. 41
2.2 Properties of Boolean Algebra	p. 43
2.2.1 Axioms	p. 43
2.2.2 Principle of Duality	p. 44
2.3 Simplification of Boolean Expressions	p. 48
2.4 Boolean Function	p. 51
2.4.1 Definitions	p. 51
2.4.2 Representations (Realization)	p. 52
2.4.3 Complement of Boolean Functions	p. 54
2.5 Circuit Analysis and Gate Design	p. 56
2.5.1 Circuit Analysis and Gate Representation	p. 56
2.5.2 Circuit Design	p. 57
2.5.3 Multiple Input Gates	p. 59
2.6 Electrical Circuits	p. 59
2.6.1 Voltage, Current, and Resistance	p. 59
2.6.2 Ohm's Law	p. 60
2.7 Kirchhoff's Laws and Voltage Division	p. 61
2.7.1 Voltage Difference	p. 61
2.7.2 Kirchhoff's Voltage Law	p. 62
2.7.3 Voltage Division	p. 63
2.8 Kirchhoff's Current Law	p. 66
2.9 RC Circuits	p. 71
2.10 Transistors and Logic Gates	p. 75
2.11 CMOS Gate Design	p. 78
2.11.1 The AND CMOS Design	p. 80
Chapter 2 Exercises	p. 83
3 Canonical Forms and Logical Completeness	p. 87
3.1 Canonical Forms of Boolean Functions	p. 88
3.1.1 Canonical Sum Form	p. 88
3.1.2 Canonical Product Form	p. 92
3.2 Sum of Product and Product of Sum Forms	p. 95
3.2.1 Sum of Product Form	p. 95
3.2.2 Product of Sum Form	p. 96
3.2.3 Verification of Function Equality Using Canonical Forms	p. 96
3.3 Design of Functions in Standard Forms	p. 98
3.3.1 Canonical Sum and Sum of Product Design	p. 98
3.3.2 Canonical Product and Product of Sum Representation	p. 100
3.4 Other Two Variable Functions	p. 100
3.4.1 Number of Boolean Functions over Two Variables	p. 101
3.4.1.1 The NAND Function	p. 101
3.4.1.2 The NOR Function	p. 101
3.4.1.3 The Exclusive OR Function	p. 102
3.4.1.4 The Equivalence Function	p. 102
3.5 Logical Completeness	p. 103
3.5.1 Definition and Examples	p. 104
3.5.2 The NAND and NOR Gates as Logically Complete Gates	p. 105
3.6 NAND and NOR Design of Combinational Circuits	p. 106
3.6.1 NAND Gate Design	p. 107
3.6.2 NOR Gate Design	p. 108
3.6.3 AND-OR-Invert and OR-AND-Invert Design	p. 111
3.7 Design Automation Tools and Levels of Abstraction	p. 111
3.7.1 Levels of Abstraction	p. 112
3.7.2 Computer-Aided Design (CAD) Tools	p. 113
3.7.2.1 Design Entry	p. 115
3.7.2.2 Synthesis	p. 115
3.7.2.3 Simulation	p. 115
3.8 Application to the Electronics Workbench (EW)	p. 116
3.8.1 The Electronics Workbench	p. 116
3.8.2 Design Entry	p. 117
3.8.2.1 Design Entry through Truth Tables	p. 117
3.8.2.2 Design Entry through Equations	p. 119
3.8.2.3 Design Entry Using Schematic Capture	p. 119
3.8.3 Synthesis	p. 122
3.8.3.1 Synthesis from Truth Table	p. 123
3.8.3.2 Synthesis from Equations	p. 123
3.8.3.3 Synthesis from Schematic Capture	p. 124
3.8.4 Simulation	p. 125
3.9 Integrated Circuits	p. 127
3.9.1 Small-Scale Integration	p. 128
3.9.2 Medium-Scale Integration	p. 128
3.9.3 Large-Scale Integration	p. 128
3.9.4 Very-Large-Scale Integration	p. 129
Chapter 3 Exercises	p. 131
4 Minimization of Boolean Functions	p. 133
4.1 Logical Adjacencies and K-Map Construction	p. 133
4.1.1 Logical Adjacency	p. 134
4.1.2 K-Map Construction	p. 135
4.1.2.1 The Inputs to the Table	p. 136
4.1.2.2 How Is the Table Read?	p. 136
4.2 Subcube Formations	p. 137
4.2.1 Filling the Table Entries	p. 137
4.2.2 Subcubes and Minimization	p. 139
4.3 K-Map Minimization	p. 142
4.3.1 Subcubes and Prime Implicants	p. 142
4.3.2 K-Map Minimization	p. 145
4.3.2.1 Relationship to Subcubes on a K-Map	p. 146
4.3.2.2 The Minimization Process	p. 148
4.3.2.3 Essential Prime Implicants and Examples	p. 148
4.4 Incompletely Specified Functions	p. 152
4.5 Product of Sum Minimization	p. 154
4.6 The Quine-McCluskey or Tabular Method	p. 156
4.6.1 Building Prime Implicants	p. 157
4.6.2 Finding Minimal Cover	p. 159
4.6.3 Algorithmic Procedure of the Tabular Method	p. 160
4.6.3.1 Forming the Prime Implicants	p. 160
4.6.3.2 Minimal Cover Procedure	p. 163
4.6.4 Decimal Method of Building Prime Implicants	p. 165
4.7 Multiple-Output Function Minimization	p. 167
Chapter 4 Exercises	p. 173
5 Arithmetic Logic Circuits and Programmable Logic Devices	p. 175
5.1 Binary Adders	p. 176
5.1.1 Iterative Circuits	p. 176
5.1.2 Half and Full Adders	p. 177
5.2 Look-Ahead Carry Generators	p. 180
5.3 Magnitude Comparators	p. 182
5.3.1 1-Bit Magnitude Comparator	p. 184
5.3.2 Boolean Equations for the Equal Output	p. 184
5.3.3 Design of the A [greater than sign] B Output	p. 185
5.3.4 Boolean Equations for A [less than sign] B	p. 186
5.3.5 Magnitude Comparators with Enable Lines	p. 186
5.4 Binary Subtractors	p. 186
5.4.1 Half Subtractors	p. 187
5.5 Arithmetic Circutis Using Radix Complement	p. 190
5.5.1 Unsigned Addition and Subtraction	p. 190
5.5.2 Hardware Implementation of Unsigned Arithmetic	p. 192
5.5.3 Signed Number Arithmetic in Radix Complement	p. 193
5.5.3.1 An Alternative Method to Compute 2's Complement	p. 193
5.5.3.2 Signed Arithmetic	p. 195
5.5.3.2.1 Case One (No Overflow or Underflow Is Possible)	p. 195
5.5.3.2.2 Case Two (Overflow Is Possible to Occur)	p. 195
5.5.3.2.3 Case Three (Underflow Is Possible to Occur)	p. 196
5.5.4 Hardware Implementation of Signed Arithmetic	p. 198
5.6 Multiplier Circuits	p. 198
5.7 Multiplexers	p. 200
5.7.1 Design of Multiple Output Multiplexers	p. 202
5.8 Design of a Simple Arithmetic Logic Unit	p. 203
5.8.1 Subtraction and the Arithmetic Unit	p. 204
5.8.2 Bit-Wise Logic Operations	p. 205
5.8.3 Combinational Shift Left	p. 206
5.8.4 The Design of the ALU	p. 206
Chapter 5 Exercises	p. 209
6 Programmable Logic Devices	p. 213
6.1 Decoders	p. 213
6.1.1 Binary Decoders	p. 214
6.1.2 Function Design Using Decoders	p. 217
6.1.3 Building Larger Decoders from Smaller Ones	p. 220
6.2 Encoders	p. 222
6.2.1 Binary Encoders	p. 223
6.2.2 Priority Encoders	p. 224
6.3 Multiplexers	p. 225
6.3.1 Design and Equations	p. 226
6.3.2 Design of Larger Multiplexers from Smaller Ones	p. 227
6.3.3 Design of Boolean Functions Using Multiplexers	p. 228
6.4 Demultiplexers	p. 231
6.5 Programmable Logic Arrays	p. 233
6.5.1 Programmable Logic Devices (PLDs)	p. 233
6.5.2 Programmable Logic Arrays	p. 234
6.5.3 Tabular Description	p. 239
6.5.4 AND-OR-NOT Design	p. 241
6.6 Programmable Array Logic Devices	p. 243
6.7 Read-Only Memory	p. 245
6.8 Diodes and Programmable Logic Devices	p. 247
6.8.1 Diodes	p. 248
6.8.2 Programmable Logic Devices	p. 250
6.8.3 Diode Design of Programmable Logic Arrays	p. 251
Chapter 6 Exercises	p. 253
7 Flip-Flops and Analysis of Sequential Circuits	p. 255
7.1 Latches	p. 256
7.1.1 Feedback Loops	p. 256
7.1.2 SR Latches	p. 257
7.2 Behavioral Description	p. 260
7.2.1 Characteristic Table	p. 260
7.2.2 Characteristic Equations	p. 261
7.2.3 State Diagrams	p. 262
7.2.4 Timing Diagrams	p. 263
7.3 Other Primitive Latches	p. 264
7.3.1 Characteristic Tables of the Three Latches	p. 265
7.3.2 The Characteristic Equations	p. 266
7.3.3 The State Diagrams	p. 266
7.4 The Latches Gate Design	p. 266
7.4.1 D Latch Design	p. 266
7.4.2 The JK Latch	p. 267
7.4.3 The T Latch	p. 269
7.5 Gated Latches	p. 270
7.6 Flip-Flops	p. 273
7.6.1 Asynchronous and Synchronous Circuits	p. 273
7.6.2 Master-Slave Flip-Flops	p. 275
7.7 Glitches and Ones-Catching	p. 277
7.8 Edge-Triggered Flip-Flops	p. 278
7.8.1 Asynchronous Preset	p. 279
7.8.2 Clock Value Equal to 1	p. 281
7.8.3 Clock Makes a Transition from 1 to 0	p. 281
7.8.4 Clock Value Is 0	p. 281
7.8.5 Clock Makes Transition from 0 to 1	p. 282
7.9 Block Diagrams and Timing Constraints	p. 283
7.9.1 Timing Constraints	p. 284
7.10 Analysis of Sequential Circuits	p. 285
7.10.1 Sequential Circuits Block Diagram Model	p. 287
7.10.2 Characteristic Equations	p. 288
7.10.3 Characteristic or State Table Construction	p. 291
7.10.4 State Diagrams	p. 291
7.10.5 Timing Diagrams	p. 294
7.10.6 Alternative Representations of State Tables	p. 298
Chapter 7 Exercises	p. 301
8 Design of Sequential Circuits and State Minimization	p. 305
8.1 Block Diagrams and Design from Excitation Equations	p. 306
8.1.1 Design of Sequential Circuits Given the External Outputs and Excitation Equations	p. 307
8.2 Design Given the Characteristic Equations	p. 308
8.2.1 Design Using D Flip-Flops	p. 309
8.2.2 Design Using JK Flip-Flops	p. 311
8.3 General Design Procedure of Sequential Circuits	p. 313
8.3.1 Step 1	p. 313
8.3.2 Step 2	p. 314
8.3.3 Step 3	p. 314
8.3.3.1 Flip-Flop Excitation Tables	p. 315
8.3.4 Step 4	p. 316
8.3.5 Step 5	p. 317
8.4 Machine Equivalence and State Assignments	p. 319
8.5 Mealy State Diagrams	p. 323
8.6 Moore Machines	p. 328
8.6.1 Conversion from Mealy to Moore Machines	p. 330
8.7 Machine and State Equivalence	p. 331
8.8 State Reduction and Minimal State Diagrams	p. 334
8.8.1 The Reduced State Table	p. 338
Chapter 8 Exercises	p. 341
9 Registers, Counters, and Memory Elements	p. 345
9.1 Registers	p. 346
9.1.1 Parallel Registers	p. 346
9.1.2 Shift Registers	p. 348
9.2 Counters	p. 351
9.2.1 Mod-2[superscript n] Synchronous Counters	p. 351
9.2.2 Mod-M Counters for General M	p. 353
9.2.3 Binary Counters with Decreasing Counts	p. 356
9.3 Asynchronous, Ring, and Johnson Counters	p. 357
9.3.1 Asynchronous Counters	p. 357
9.3.2 Ring Counters	p. 359
9.3.3 Johnson Counters	p. 360
9.4 General-Purpose Register-Counter Circuits	p. 361
9.5 Memory Block Diagram	p. 366
9.6 Building Larger RAM from Smaller RAM	p. 368
9.7 The Data Bus Connections	p. 372
9.7.1 Connections Using Multiplexers	p. 372
9.7.2 Connections Using Tristate Gates	p. 374
9.8 Internal Design of Memory	p. 374
9.8.1 Gate Design of a Single Memory Cell	p. 375
9.8.2 RAM Design with Two Data Buses	p. 376
9.8.3 RAM Design with a Single Data Bus	p. 378
9.9 Register Files	p. 380
Chapter 9 Exercises	p. 387
10 Instruction Set Architecture	p. 391
10.1 Instruction Set of a Computer	p. 391
10.2 Accumulator-Based Instruction Set Architecture	p. 392
10.2.1 Accumulator-Based Architecture	p. 393
10.2.2 Accumulator-Based Instructions	p. 394
10.2.2.1 Load and Store Instructions	p. 394
10.2.2.2 Arithmetic and Logic Instructions	p. 395
10.2.2.3 Register Transfer Languages	p. 396
10.3 General Register-Based Architecture	p. 398
10.4 Machine-Level Instructions	p. 400
10.5 The Computer Instruction Cycles	p. 403
10.6 Common Addressing Modes	p. 405
10.7 Macros	p. 410
Chapter 10 Exercises	p. 413
11 Design of a Simple AC-Based CPU	p. 417
11.1 Microoperation and Register Transfer Languages	p. 418
11.2 Design of RTL Statements	p. 420
11.3 Instruction Set of the Simple CPU	p. 424
11.3.1 Instruction Set Completeness	p. 424
11.3.1.1 Arithmetic Instructions	p. 425
11.3.1.2 Logic Instructions	p. 425
11.3.1.3 Branch (Jump Instructions)	p. 425
11.3.1.4 CPU and Memory Instructions	p. 425
11.3.2 The Instruction Set of the Simple CPU	p. 425
11.4 CPU Organization Data Path	p. 427
11.5 The Control Unit	p. 430
11.6 The Three Cycles	p. 431
11.7 Computer Cycles Execute Microoperations	p. 433
11.7.1 The Memory-Reference Instructions	p. 433
11.7.1.1 The LW Instruction	p. 433
11.7.1.2 The ST Instruction	p. 434
11.7.1.3 The ADD Instruction	p. 434
11.7.1.4 The AND Instruction	p. 435
11.7.1.5 The JMP Instruction	p. 435
11.7.1.6 The SKZ and the SKP Instructions	p. 435
11.7.2 Register-Reference Instructions	p. 435
11.8 Inputs and Outputs of the Combinational Part of Control Unit	p. 437
11.8.1 Input Part	p. 437
11.8.2 Output Part	p. 437
11.9 The Control Unit Output Functions	p. 439
11.10 Design of the AC-Based CPU	p. 441
Chapter 11 Exercises	p. 445
Appendix A References	p. 447
Appendix B Answers to Selected Problems	p. 449
Index	p. 473

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