ESD : design and synthesis

Title:

Personal Author:

Voldman, Steven H.

Publication Information:

Chichester, West Sussex, U.K. : Wiley, 2011

Physical Description:

xx, 270 p. : ill. ; 25 cm.

ISBN:

9780470685716

Abstract:

"The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip. It enables ESD engineers to build better products by exploring six key areas- 1) ESD design synthesis 2) I/O design and integration 3) semiconductor chip architecture 4) floor planning 5) power bus design and 6) ESD power clamps. The book is well organised and uses a top down approach, starting by looking at the basics. It takes a look at design synthesis, floor planning and ESD design issues. The book analyses the synthesis of device elements, also the synthesis of ESD circuits and functional circuits. In Chapter 5, the synthesis of ESD power clamps is described, followed by coverage on synthesis of power rails with I/O, ESD and pads in Chapter 6. The integration of special function circuits and special issues is helpfully included in the book before more broad ESD design methodioligies are outlined. The important areas of design rule checking, along with design verification methods, are looked at towards the end of the book, and the last chapter provides the reader with knowledge about useful design tools. In many ways this text is unique. There is currently no other book on the market that addresses ESD design synthesis and its relationaship to the characterisation of test structures and technologies. Focuses on practical design techniques, providing good design practices and rules contains essential information on chip floor-planning and architecture that has not been published in a single book before covers up-to-date technology benchmarking and characterisation uses state-of-the-art examples with detailed discussion includes end-of-chapter design and integration problems"-- Provided by publisher.

"The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip"-- Provided by publisher.

Subject Term:

Semiconductors -- Protection

Integrated circuits -- Protection

Electrostatics

Analog electronic systems -- Design and construction

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Summary

Electrostatic discharge (ESD) continues to impact semiconductor components and systems as technologies scale from micro- to nano-electronics.

This book studies electrical overstress, ESD, and latchup from a whole-chip ESD design synthesis approach. It provides a clear insight into the integration of ESD protection networks from a generalist perspective, followed by examples in specific technologies, circuits, and chips. Uniquely both the semiconductor chip integration issues and floorplanning of ESD networks are covered from a 'top-down' design approach.

Look inside for extensive coverage on:

integration of cores, power bussing, and signal pins in DRAM, SRAM, CMOS image processing chips, microprocessors, analog products, RF components and how the integration influences ESD design and integration architecturing of mixed voltage, mixed signal, to RF design for ESD analysis floorplanning for peripheral and core I/O designs, and the implications on ESD and latchup guard ring integration for both a 'bottom-up' and 'top-down' methodology addressing I/O guard rings, ESD guard rings, I/O to I/O, and I/O to core classification of ESD power clamps and ESD signal pin circuitry, and how to make the correct choice for a given semiconductor chip examples of ESD design for the state-of-the-art technologies discussed, including CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, and smart power practical methods for the understanding of ESD circuit power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics

ESD: Design and Synthesis is a continuation of the author's series of books on ESD protection. It is an essential reference for: ESD, circuit, and semiconductor engineers; design synthesis team leaders; layout design, characterisation, floorplanning, test and reliability engineers; technicians; and groundrule and test site developers in the manufacturing and design of semiconductor chips.

It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, and manufacturing sciences, and on courses involving the design of ESD devices, chips and systems. This book offers a useful insight into the issues that confront modern technology as we enter the nano-electronic era.

Author Notes

Dr. Steven H. Voldman, IEEE Fellow, Vermont, USA
Prolific Wiley writer, Dr. Steven Voldman has been involved with ESD work since 1991. He has been Chairman of the ESD Association WG 5.5 on TLP testing since 2001 and he was Chairman of the SEMATECH ESD Working Group on ESD Technology from 1995 until 1998.
Dr. Voldman worked 25 years at IBM before working at Qimonda in 2007 and then TSMC Corporation in 2008. Currently he holds 181 patents in the areas of ESD and latchup, and has 125 pending. His fields of expertise are electrostatic discharge (ESD) protection, latchup, ESD testing and ESD design. To date he has worked on many design architectures from SRAM, DRAM, ASICs, Microprocessors, NVRAMs, image processing designs and power technology.

About the Author

Preface

Acknowledgements

Chapter 1 ESD Design Synthesis Basics

1.1 ESD Design Synthesis and Architecture Flow

1.2 ESD Design - The Signal Path and Alternate Current Path

1.3 ESD Electrical Circuit and Schematic Architecture Concepts

1.4 Mapping Semiconductor Chips and ESD Design

1.5 ESD Chip Architecture and ESD Test Standards

1.6 ESD Testing

1.7 ESD Chip Architecture and Alternative Current Path

1.8 ESD Networks, Sequencing and Chip Architecture

1.9 Latchup-free ESD Networks

1.10 ESD Design Concepts - Buffering Inter-device

1.11 ESD Design Concepts - Ballasting Inter-device

1.12 ESD Design Concepts - Ballasting Intra-device

1.13 ESD Design Concepts - Distributed Load Techniques

1.14 ESD Design Concepts - Dummy Circuits

1.15 ESD Design Concepts - Power supply De-coupling

1.16 ESD Design Concepts - Feedback Loop De-coupling

1.17 ESD Layout and Floorplan Related Concepts

1.18 ESD Design Concepts - Analog Design

1.19 ESD Design Concepts - Wire Bonds

1.20 ESD Computer Aided Design

1.21 Summary and Closing Comments

Problems

References

2 Chapter 2 ESD Architecture and Floorplanning

2.1 ESD Design Floor plan

2.2 Peripheral I/O Design

2.3 Lumped ESD Power Clamp in Peripheral I/O Design Architecture

2.4 Lumped ESD Power Clamp in Peripheral I/O Design Architecture - Master/slave ESD Power Clamp System

2.5 Array I/O

2.6 ESD Architecture - Dummy Bus Architecture

2.7 Native Voltage Power Supply Architecture

2.8 Mixed Voltage Architecture

2.9 Mixed Signal Architecture

2.10 Mixed Signal Architecture - Digital and Analog CMOS

2.11 Mixed Signal Architecture - Digital, Analog and RF Architecture

2.12 Summary and Closing Comments

Problems

References

3 Chapter 3 ESD Power Grid Design and Synthesis

3.1 ESD Power Grid

3.2 Semiconductor Chip Impedance

3.3 Interconnect Failure and Dynamic On-Resistance

3.4 Interconnect Wire and Via Guidelines

3.5 ESD Power Grid Resistance

3.6 Power Grid Layout Design

3.7 ESD Specification Power Grid Considerations

3.8 Power Grid Design Synthesis - ESD Design Rule Checking (DRC) Methods

3.9 Summary and Closing Comments

Problems

References

4 Chapter 4 ESD Power Clamp Design and Synthesis

4.1 ESD Power Clamps

4.2 Design Synthesis of ESD Power Clamps

4.3 Design Synthesis of ESD Power Clamps - The ESD Power Clamp Shunting Element

4.4 ESD Power Clamp Issues

4.5 ESD Power Clamp Design - MOSFET Power Clamp

4.6 ESD Power Clamp Design Synthesis - Bipolar ESD Power Clamps

4.7 Master/Slave ESD Power Clamp Systems

4.8 Summary and Closing Comments

Problems

References

Chapter 5 ESD Signal Pin Network Design and Synthesis

5.1 ESD Signal Pin Structures

5.2 ESD Signal Pin Structures - ESD and Bond Pad Layout

5.3 ESD Design Synthesis and Layout of MOSFETs

5.4 ESD Design Synthesis and Layout of Diodes

5.5 ESD Design Synthesis of Silicon Controlled Rectifiers (SCR)

5.6 ESD Design Synthesis and Layout of Resistors

5.7 ESD Design Synthesis of Inductors

5.8 Summary and Closing Comments

Problems

References

Chapter 6 Guard Ring Design and Synthesis

6.1 Guard Ring Design and Integration

6.2 Guard Ring Characterization

6.3 Semiconductor Chip Guard Ring Seal

6.4 I/O to Core Guard Rings

6.5 I/O to I/O Guard Rings

6.6 Within I/O Guard Rings

6.7 ESD Signal Pin Guard Rings

6.8 Library Element Guard Rings

6.9 Mixed Signal Guard Rings - Digital to Analog

6.10 Mixed Voltage Guard Rings - High Voltage to Low Voltage

6.11 Passive and Active Guard Rings

6.12 Trench Guard Rings

6.13 Through Silicon Via (TSV) Guard Rings

6.14 Guard Ring Design Rule Checking (DRC)

6.15 Guard Ring and Computer Aided Design (CAD) Methods

6.16 Summary and Closing Comments

Problems

References

Chapter 7 ESD Full Chip Design Integration and Architecture

7.1 Design Synthesis and Integration

7.2 Digital Design

7.3 Custom Design versus Standard Cell Design

7.4 Memory ESD Design

7.5 Microprocessor ESD Design

7.6 Application Specific Integrated Circuits (ASICs)

7.7 CMOS Image Processing Chip Design

7.8 Mixed Signal Architecture

7.9 Summary and Closing Comments

Problems

References

Index

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Summary

Summary

Author Notes

Table of Contents