Using altera DE1-SoC: hard processor system (HPS) and field programmable gate array (FPGA) cores for median filter

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Title:

Using altera DE1-SoC: hard processor system (HPS) and field programmable gate array (FPGA) cores for median filter

Personal Author:

Syed Ahmad Asyraf Syed Mustafa, 1995- , author

Physical Description:

axv, 47 pages : illustrations (some colors) ; 30 cm

General Note:

Also available in CD-ROM : CP 080823 ra

Fulltext is available at http://dms.library.utm.my:8080

Supervisor : Mr. Izam Kamisian

Subject Term:

Image processing -- Digital techniques

Added Author:

Added Corporate Author:

Fakulti Kejuruteraan Elektrik

DSP_DISSERTATION:

Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2018

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... FKE Library	32030000001829	TA1637 S93 2018 raf	Closed Access Thesis	UTM Project Paper (Open Shelves)	Searching... Unknown
Searching... Perpustakaan Raja Zarith Sofiah	35000000008760	TA1637 S93 2018 raf	Closed Access Thesis	UTM Project Paper (Closed Access)	Searching... Unknown

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