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Cover image for Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
Title:
Field programmable gate array based convolution neural network hardware accelerator with optimized memory controller
Physical Description:
xv, 110 pages: illustrations ; 27 cm
General Note:
Also available in CD-ROM : CP 084370 ra

Fulltext is available at http://dms.library.utm.my:8080

Supervisor : Mohd. Shahrizal Rusli
Added Author:
DSP_DISSERTATION:
Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Sistem Mikroelektronik)) - Universiti Teknologi Malaysia, 2020

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35000000029159 XX(889001.2) Closed Access Thesis UTM Master Thesis (Closed Access)
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