Wael BadawyJohn V MccannyEarl E. Swartzlander, Jr.Ludovic Loiseau and Yvon SavariaLuc Charest and El Mostapha AboulhamidSebastien Regimbal and Jean-FrancoisLemire and Yvon Savaria and Guy Bois and El Mostapha Aboulhamid and Andre BaronI. Skliarova and A.B. FerrariGiuseppe Ascia and Vincenzo Catania and Maurizio PalesiKhaled M. ElleithyEmil DumitrescuMakarand Joshi and Ashok KumarL. Hong and M. Nahvi and R. Fung and A. Ivanov and R. SalehHenry Fu and Richard F. HobsonMohamed Abd El-Salam and Ashraf Salem and Gamal AlyValery SklyarovLilian Bossuet and Guy Gogniat and Jean-Philippe Diguet and Jean-Luc PhilippeLuc Filion and Jerome Chevalier and Guy Bois and El Mostapha AboulhamidMaghsoud Abbaspour and Jianwen ZhuJari Heikkinen and Jarmo Takala and Jaakko SertamoV. Cheushev and J. Kolodziejczyk and T. Luba and C. Moraga and P. Sapiecha and V. Shmerko S. YanushkevichBruce F. CockburnJarno Vanne and Eero Aho and Kimmo Kuusilinna and Timo HamalainenEero Aho and Jarno Vanne and Kimmo Kuusilinna and Timo HamalainenMohammed Sayed and Wael BadawyGauthier Lafruit and Jan BormansDusan Suvakovic and C. Andre T. SalamaSanghoon Joo and Minkyu Song and Hyunyeon Cho and Sangki KimMohamed I. Sobhy and Mohammed A. Aseeri and Alaa E. R. ShehataMohammed Sayed and Wael BadawyYoon-Sik Son and Jong-Wha ChongNeal K. Bambha and S.S. BhattacharyyaW.C. Lo and A.T. Erdogan and T.ArslanMagdy BayoumiMagdy A. El-Moursy and Eby G. FriedmanShizhong Mei and Yehea I. IsmailWalied A. MoussaSazzadur Chowdhury and M. Ahmadi and G. A. Jullien and W. C. MillerHesham Ahmed and Walied Moussa and Wael BadawyRafik S. GuindiWalid Abdel-Hamid and Aboelmagd Noureldin and Dr. Naser El-Sheimy and Dr. Gerard Lachapellee

Preface	p. xi
Acknowledgements	p. xiii
Contributors	p. xv
Chapter 1 Introduction	p. 1
System on Chip: The Challenge and Opportunities	p. 3
Electronic Product Innovation Direct Mapped Signal Processing SoC Cores	p. 17
System-On-Chip Implementation Of Signal Processors	p. 26
Chapter 2 Design Reuse	p. 29
Methodologies and Strategies for Effective Design-Reuse	p. 31
A VHDL/SystemC Comparison in Handling Design Reuse	p. 41
Aspect Partitioning for Hardware Verification Reuse	p. 51
Reconfigurable Combinatorial Accelerators for Real Time Processing	p. 61
Tuning Methodologies for Parameterized Systems Design	p. 71
Chapter 3 Testand Verification	p. 83
Formal Verifications of Systems on Chips: Current and Future Directions	p. 85
A Practical Approach to the Formal Verification of SoC's with Symbolic Model-Checking	p. 98
High Performance Verification Solutions for SOC Designs	p. 111
Novel Test Methodologies for SoC/IP Design: Implementation and Comparison	p. 125
Chapter 4 Modeling	p. 137
SOC Modeling and Simulation Based on Java	p. 139
RTOS Modeling Using SystemC	p. 150
Modeling, Synthesis and Implementation of Communicating Hierarchical FSM	p. 160
A Modeling Method for Reconfigurable Architectures	p. 170
Chapter 5 Design Techniques	p. 181
The Syslib-Picasso Methodology for the Co-Design Specification Capture Phrase	p. 183
Automatic Porting Of Binary File Descriptor Library	p. 193
Code Compression on Transport Triggered Architectures	p. 203
An Approach To Flexible Multi-Level Network Design	p. 214
Chapter 6 Memory	p. 225
Survey of Emerging Nonvolatile Embedded Memory Technologies	p. 227
Configurable Parallel Memory Implementation For System-on-Chip Designs	p. 237
XOR-scheme Implementations In Configurable Parallel Memory	p. 249
An Novel Low Power Embedded Memory Architecture for MPEG-4 Applications with Mobile Devices	p. 262
Assessment of MPEG-4 VTC and JPEG2000 Dynamic Memory Requirements	p. 273
Chapter 7 Circuit Techniques	p. 285
Modified Distributed Arithmetic Architecture for Adiabatic DSP Systems	p. 287
Design of a CMOS Wide Range Logarithmic Amplifier with a Modified Parallel Architecture	p. 296
Digital Hardware Implementation of Continuous & Discrete Chaotic Generators	p. 305
Novel 1-Bit Full Adder Cells For Low-Power System-On-Chip Applications	p. 314
Chapter 8 Low Power	p. 325
A New Logic Method for considering Low Power and High Testibility	p. 327
System Synthesis for Optically-Connected, Multiprocessors On-chip	p. 339
Low Power System On Chip Platform Architecture for High Performance Applications	p. 349
Chapter 9 Interconnect and Technology	p. 357
SOC Interconnect in Deep Submicron	p. 359
Optimizing Inductive Interconnect for Low Power	p. 380
Skin Effects in System on a Chip Interconnects	p. 392
Chapter 10 Micro Electro Mechanical Systems	p. 403
Road Map Towards Designing MEMS Devices with High-Reliability	p. 405
A Mems Socket Interface For Soc Connectivity	p. 411
On the Application of Finite Element to Investigate the Reliability of Electrostatic Comb-Drive Actuators Utilized in Micro-Fluidic and Space Systems	p. 422
An HDL Model For A Vacuum-Sealed Micromachined Pressure Sensor	p. 429
Performance Analysis of MEMS-based Inertial Sensors for Positioning Applications	p. 440
Index	p. 451