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Cover image for Generating hardware assertion checkers : for hardware verification, emulation, post-fabrication debugging and on-line monitoring
Title:
Generating hardware assertion checkers : for hardware verification, emulation, post-fabrication debugging and on-line monitoring
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Publication Information:
Berlin, GW : Springer, 2008
Physical Description:
xx, 279 p. : ill. ; 24 cm.
ISBN:
9781402085857
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30000010197643 TK7874.58 B67 2008 Open Access Book Book
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Summary

Summary

Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity.

This is the first book that presents an "under-the-hood" view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.


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