Title:
FPGA design using verilog - HDL of A 16 bit risc processor
Personal Author:
Publication Information:
2005
Physical Description:
xvii, 120 p. : ill. ; 30 cm.
General Note:
Supervisor : Prof. Dr. Mohamed Khalil Hj. Mohd. Hani
Added Author:
Added Corporate Author:
DSP_DISSERTATION:
Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2005
Available:*
Library | Item Barcode | [[missing key: search.ChildField.CALLNUMBER]] | Material Type | Item Category 1 | Status |
---|---|---|---|---|---|
Searching... | FKE30000001667 | Closed Access Thesis | UTM Project Paper (Closed Access) | Searching... | |
Searching... | 30000010096294 | TK7895.G36 J63 2005 raf | Closed Access Thesis | UTM Project Paper (Closed Access) | Searching... |