Using altera DE1-SoC: hard processor system (HPS) and field programmable gate array (FPGA) cores for median filter

Title:

Personal Author:

Physical Description:

1 computer disc (CD-ROM) ; 12 cm

General Note:

Also available in printed version : TA1637 S93 2018 raf

Supervisor : Mr. Izam Kamisian

Subject Term:

DSP_DISSERTATION:

Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2018

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