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Cover image for Reconfigurable computing : architectures, tools, and applications : third international workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007 : proceedings
Title:
Reconfigurable computing : architectures, tools, and applications : third international workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007 : proceedings
Series:
Lecture notes in computer science, 4419
Publication Information:
Berlin : Springer, 2007
ISBN:
9783540714309
General Note:
Available online version
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Electronic Access:
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30000010139613 QA76.9.A3 A66 2007 Open Access Book Proceedings, Conference, Workshop etc.
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Summary

Summary

This book constitutes the refereed proceedings of the Third International Workshop on Applied Reconfigurable Computing, ARC 2007, held in Mangaratiba, Brazil, in March 2007. The 27 full papers and 10 short papers presented together with a late-comer contribution from ARC 2006 are organized in topical sections on architectures, mapping techniques and tools, arithmetic, and applications.


Table of Contents

Frank Bouwens and Mladen Berekovic and Andreas Kanstein and Georgi GaydadjievMazen A.R. Saghir and Rawan NaousKehuai Wu and Andreas Kanstein and Jan Madsen and Mladen BerekovicJe-Hoon Lee and Seung-Sook Lee and Kyoung-Rok ChoJae Young Hur and Stephan Wong and Stamatis VassiliadisJae Young Hur and Todor Stefanov and Stephan Wong and Stamatis VassiliadisSaar DrimerJae-Jin Lee and Dong-Guk Hwang and Gi-Yong SongKostas Siozios and Stelios Mamagkakis and Dimitrios Soudris and Antonios ThanailakisJoonseok Park and Pedro C. DinizYazhuo Dong and Yong Dou and Jie ZhouRainer ScholzCarlo Galuzzi and Keen Bertels and Stamatis VassiliadisKazunori Matsuyama and Motoki Amagasaki and Hideaki Nakayama and Ryoichi Yamaguchi and Masahiro Iida and Toshinori SueyoshiYong Dou and Jinhui Xu and Guiming WuCesar Torres-Huitzil and Bernard Girau and Adrien GauffriauJoao Bispo and Ioannis Sourdis and Joao M.P. Cardoso and Stamatis VassiliadisNicolas Herve and Daniel Menard and Olivier SentieysRuzica Jevtic and Carlos Carreras and Gabriel CaffarenaJean-Luc Beuchat and Takanori Miyoshi and Yoshihito Oyama and Eiji OkamotoFrancisco Rodriguez-Henriquez and Guillermo Morales-Luna and Nazar A. Saqib and Nareli Cruz-CortesEdgar Ferrer and Dorothy Bollman and Oscar MorenoRayan Chikhi and Steven Derrien and Auguste Noumsi and Patrice QuintonJavier Diaz and Eduardo Ros and Sonia Mota and Richard CarrilloGuenter KnittelYong-Min Lee and Chang-Seok Choi and Seung-Gon Hwang and Hyun Dong Kim and Chul Hong Min and Jae-Hyun Park and Hanho Lee and Tae Seon Kim and Chong-Ho LeeXiaodong Yang and Shengmei Mou and Yong DouDavid B. Thomas and Wayne Luk and Michael StumpfNilton B. Armstrong Jr. and Heitor S. Lopes and Carlos R. Erig LimaEdson P. Ferlin and Heitor S. Lopes and Carlos R. Erig Lima and Ederson CichaczewskiSonia Mota and Eduardo Ros and Javier Diaz and Rafael Rodriguez and Richard CarrilloShinya Hiramoto and Masaki Nakanishi and Shigeru Yamashita and Yasuhiko NakashimaSeamas McGettrick and Dermot Geraghty and Ciaran McElroyYoshiki Yamaguchi and Kenji Kanazawa and Yoshiharu Ohke and Tsutomu MaruyamaMatteo Tomasi and Javier Diaz and Eduardo RosPatrick Rocke and Brian McGinley and Fearghal Morgan and John MaherCarlos R. Erig Lima and Heitor S. Lopes and Maiko R. Moroz and Ramon M. MenezesWagner R. Weinert and Cesar Benitez and Heitor S. Lopes and Carlos R. Erig Lima
Architectures [Regular Papers]
Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Arrayp. 1
A Configurable Multi-ported Register File Architecture for Soft Processor Coresp. 14
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecturep. 26
Asynchronous ARM Processor Employing an Adaptive Pipeline Architecturep. 39
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAsp. 49
Systematic Customization of On-Chip Crossbar Interconnectsp. 61
Authentication of FPGA Bitstreams: Why and Howp. 73
Architectures [Short Papers]
Design of a Reversible PLD Architecturep. 85
Designing Heterogeneous FPGAs with Multiple SBsp. 91
Mapping Techniques and Tools [Regular Papers]
Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementationsp. 97
Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardwarep. 110
Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementationsp. 122
A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructionsp. 130
Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mappingp. 142
The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipeliningp. 155
Hardware/Software Codesign for Embedded Implementation of Neural Networksp. 167
Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issuesp. 179
Mapping Techniques and Tools [Short Papers]
About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizationsp. 191
Arithmetic [Regular Papers]
Switching Activity Models for Power Estimation in FPGA Multipliersp. 201
Multiplication over F[subscript p]m on FPGA: A Surveyp. 214
A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithmp. 226
A Fast Finite Field Multiplierp. 238
Applications [Regular Papers]
Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrievalp. 247
Image Processing Architecture for Local Features Computationp. 259
A Compact Shader for FPGA-Based Volume Rendering Acceleratorsp. 271
Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applicationsp. 283
FPGA-Accelerated Molecular Dynamics Simulations: An Overviewp. 293
Reconfigurable Hardware Acceleration of Canonical Graph Labellingp. 302
Reconfigurable Computing for Accelerating Protein Folding Simulationsp. 314
Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuitsp. 326
Applications [Short Papers]
A Space Variant Mapping Architecture for Reliable Car Segmentationp. 337
A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheadsp. 343
Searching the Web with an FPGA Based Search Enginep. 350
An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemmap. 358
Real Time Architectures for Moving-Objects Trackingp. 365
Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controllerp. 373
Multiple Sequence Alignment Using Reconfigurable Computingp. 379
Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computingp. 385
Author Indexp. 391
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