Title:
Advanced digital logic design using verilog, state machines, and synthesis for FPGAs
Personal Author:
Publication Information:
Ontario, Canada : Thomson, 2006
ISBN:
9780534551612
Available:*
Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
|---|---|---|---|---|---|
Searching... | 30000004610576 | TK7868.L6 L435 2006 | Open Access Book | Book | Searching... |
Searching... | 30000010155599 | TK7868.L6 L435 2006 | Open Access Book | Book | Searching... |
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Summary
Summary
This textbook is intended to serve as a practical guide for the design of complex digital logic circuits such as digital control circuits, network interface circuits, pipelined arithmetic units, and RISC microprocessors. It is an advanced digital logic design textbook that emphasizes the use of synthesizable Verilog code and provides numerous fully worked-out practical design examples including a Universal Serial Bus interface, a pipelined multiply-accumulate unit, and a pipelined microprocessor for the ARM THUMB architecture.
Table of Contents
| Preface |
| Chapter 1 Condensed Overview of Introductory Digital Logic Design |
| 1.1 Number Formats |
| 1.2 Combinational Logic |
| 1.2.1 Combinational Logic Devices |
| 1.2.2 Combinational Logic Circuit Design |
| 1.3 Sequential Logic |
| 1.3.1 Sequential Logic Devices |
| 1.3.2 Synchronous Sequential Circuit Design |
| 1.3.3 Hazards and Glitches |
| 1.3.4 Mestastability |
| Chapter 2 Digital Logic Design Using Hardware Description Languages |
| 2.1 Hardware Description Languages |
| 2.2 Design Flow |
| 2.3 Synthesis |
| 2.4 Register Transfer Level Notation |
| 2.5 Logic Simulation |
| 2.6 Properties of Actual Circuits |
| Chapter 3 Introduction to Verilog and Test Benches |
| 3.1 Overview |
| 3.2 Verilog Basics |
| 3.2.1 The Module Definition |
| 3.2.2 Signals and Operators |
| 3.2.3 Structural and Behavioral Descriptions |
| 3.3 Testing and the Test Bench |
| 3.3.1 Manufacturing Testing |
| 3.3.2 Functional Testing |
| 3.3.3 Test Benches |
| 3.4 More Advanced Verilog Concepts |
| 3.4.1 Concurrent and Sequential Verilog |
| 3.4.2 Delay Modeling |
| 3.4.3 Different Types of Assignment Statements |
| 3.4.4 Parameters and Modeling a Bidirectional Bus |
| 3.4.5 Tasks and Functions |
| 3.5 Construction of Complete Verilog Programs |
| 3.5.1 Combinational Logic Circuits |
| 3.5.2 Sequential Logic Circuits |
| 3.5.3 Behavioral Modeling of More Complex Circuits |
| Chapter 4 High-Level Verilog Coding for Synthesis |
| 4.1 Register Transfer Level Notation |
| 4.2 Combinational Logic Synthesis |
| 4.2.1 Using Continuous Assignment for Combinational Logic |
| 4.2.2 Using Always Blocks for Combinational Logic |
| 4.2.3 Complex Combinational Logic Example |
| 4.3 Sequential Logic Synthesis |
| 4.4 Synthesis Heuristics |
| 4.5 Synthesis Using a Commercial Tool |
| 4.6 High-Level Verilog Coding |
| Chapter 5 State Machine Design |
| 5.1 Manual State Machine Design |
| 5.1.1 Pseudocode |
| 5.1.2 RTL Program |
| 5.1.3 Datapath |
| 5.1.4 State Diagram |
| 5.1.5 Control Logic |
| 5.1.6 State Machine Design Using ASM Charts |
| 5.2 Automatic Synthesis-Based State Machine Design |
| 5.2.1 Automatic Synthesis-Based Design Procedure |
| 5.2.2 Algorithm to HDL Code Conversion |
| 5.3 Design Example: Vending Machine |
| 5.3.1 Automatic State Machine Design for a Vending Machine |
| 5.3.2 Manual State Machine Design for a Vending Machine |
| 5.3.3 Timing Diagram |
| 5.3.4 Correspondence Between Automatic and Manual Designs |
| 5.4 Design Example: LCD Controller |
| 5.4.1 Target LCD Module |
| 5.4.2 Verilog Solution |
| Chapter 6 FPGA and Other Programmable Logic Devices |
| 6.1 Programmable Logic Devices |
| 6.1.1 Circuit Customization |
| 6.1.2 Programmable Logic Arrays |
| 6.1.3 Programmable Read Only Memories |
| 6.1.4 Programmable AND-Array Logic |
| 6.2 Field Programmable Gate Arrays |
| 6.2.1 Gate Arrays |
| 6.2.2 FPGA Overview |
| 6.2.3 Xilinx FPGA Example |
| 6.2.4 FPGA Configuration |
| 6.2.5 Xilinx Spartan-II FPGA Configuration Example |
| 6.2.6 Boundary Scan |
| Chapter 7 Design of a USB Protocol Analyzer |
| 7.1 Overview of USB Full-Speed Mode |
| 7.1.1 Packet Transfer Protocol |
| 7.1.2 Initialization Sequence |
| 7.1.3 Physical Layer Interface |
| 7.1.4 USB Packets |
| 7.1.5 Cyclic Redundancy Checks |
| 7.1.6 Observation of Actual USB Signals |
| 7.2 Design Overview |
| 7.2.1 State Machine |
| 7.2.2 Subcircuit Partitioning |
| 7.3 Verilog Solution |
| 7.3.1 Digital Phase Locked Loop |
| 7.3.2 NRZI-to-Binary Converter |
| 7.3.3 CRC Checker Submodules |
| 7.3.4 Packet ID Recognizer |
| 7.3.5 State Machine Subcircuit |
| 7.3.6 Top-Level Module |
| 7.3.7 Test Bench Code for Entire Circuit |
| 7.4 Simulation Results |
| Chapter 8 Design of Fast Arithmetic Units |
| 8.1 Adder Designs |
| 8.1.1 Ripple Carry adder |
| 8.1.2 Carry Lookahead Adder |
| 8.1.3 Carry Save Adder |
| 8.2 Multiplier Designs |
| 8.2.1 Combinational Multiplier |
| 8.2.2 Sequential Multiplier |
| 8.2.3 Fast Multiplication |
| 8.2.4 Multiply-Accumulate Units |
| 8.3 Pipelined Functional Units |
| 8.3.1 Introduction to Pipelining |
| 8.3.2 Pipelined Multiply-Accumulate Units |
| 8.4 HDL Implementations |
| 8.4.1 HDL Implementation Overview |
| 8.4.2 HDL Design for a Pipelined Multiply-Accumulate Unit |
| 8.4.3 Test Bench and Simulation Results |
| Chapter 9 Design of a Pipelined RISC Microprocessor |
| 9.1 Introduction to Microprocessors |
| 9.1.1 Reduced Instruction Set Computers |
| 9.1.2 Basic Computer Operation |
| 9.2 The THUMB Micro |
