CMOS cascade sigma-delta modulators for sensors and telecom : error analysis and practical design

Title:

Publication Information:

Dordrecht : Springer, 2006

ISBN:

9781402047756

Subject Term:

Metal oxide semiconductors, Complementary

Application-specific integrated circuit

Added Author:

Rio, R. del

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010113172	TK7871.99.M44 C57 2006	Open Access Book	Book	Searching... Unknown

CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design starts with a tutorial presentation of the fundamentals of low-pass sigma-delta modulators, their applications, and their most common architectures. It then presents an exhaustive analysis of SC circuit errors with a twofold outcome. On the one hand, compact expressions are derived to support design plans and quick top-down design. On the other, detailed behavioral models are presented to support accurate verification. This set of models allows the designer to determine the required specifications for the different modulator building blocks and form the basis of a systematic design approach. The book is completed in subsequent chapters with the detailed presentation of three high-performance modulator ICs: the first two are intended for DSL-like applications, whereas the third one is intended for automotive sensors.

CMOS Cascade Sigma-Delta Modulators forSensors and Telecom: Error Analysis and Practical Design contains highly valuable information that is structured to give the reader the necessary insight on how to design SC sigma-delta modulators.

List of Abbreviations	p. xi
Preface	p. xv
Chapter 1 ¿¿ ADCs: Principles, Architectures, and State of the Art	p. 1
1.1 Analog-to-Digital Conversion: Fundamentals	p. 2
1.1.1 Sampling	p. 3
1.1.2 Quantization	p. 3
1.2 Oversampling ¿¿ ADCs: Fundamentals	p. 7
1.2.1 Oversampling	p. 7
1.2.2 Noise-shaping	p. 8
1.2.3 Basic architecture of oversampling ¿¿ ADCs	p. 11
1.2.4 Performance metrics	p. 15
1.2.5 Ideal performance	p. 17
1.3 Single-Loop ¿¿ Architectures	p. 20
1.3.1 1st-order ¿¿ modulator	p. 20
1.3.2 2nd-order ¿¿ modulator	p. 24
1.3.3 High-order ¿¿ modulators	p. 27
Stability concerns	p. 27
Optimized NTF s	p. 28
High-order topologies	p. 31
Non-linear stabilization techniques	p. 33
1.4 Cascade ¿¿ Architectures	p. 34
1.5 Multi-Bit ¿¿ Architectures	p. 43
Influence of DAC errors	p. 45
1.5.1 Element trimming and analog calibration	p. 46
1.5.2 Digital correction	p. 47
1.5.3 Dynamic element matching	p. 48
1.5.4 Dual-quantization	p. 49
Leslie-Singh architecture	p. 49
Single-loop ¿¿Ms	p. 50
Cascade ¿¿Ms	p. 50
1.6 Parallel ¿¿ Architectures	p. 52
1.6.1 Frequency division multiplexing	p. 53
1.6.2 Time division multiplexing	p. 53
1.6.3 Code division multiplexing	p. 54
1.7 State of the Art in ¿¿ ADCs	p. 54
1.8 Summary	p. 65
Chapter 2 Non-Ideal Performance of ¿¿ Modulators	p. 67
2.1 Integrator Leakage	p. 68
Leaky integrator	p. 68
2.1.1 Single-loop ¿¿ modulators	p. 69
1st-order loop	p. 69
2nd-order loop	p. 70
Lth-order loops	p. 71
2.1.2 Cascade ¿¿ modulators	p. 72
2.2 Capacitor Mismatch	p. 77
2.2.1 Single-loop ¿¿ modulators	p. 77
2nd-order loop	p. 77
Lth-order loops	p. 78
2.2.2 Cascade ¿¿ modulators	p. 79
2.3 Integrator Setting Error	p. 83
2.3.1 Model for the transient response of SC integrators	p. 84
SC integrator model	p. 84
Transient during integration	p. 85
Transient during sampling	p. 88
Integration-sampling process	p. 91
2.3.2 Validation of the proposed model	p. 92
Comparison with experimental results	p. 92
Comparison with traditional models	p. 93
2.3.3 Effect of the amplifier finite gain-bandwidth product	p. 95
Single-loop ¿¿ modulators	p. 97
Cascade ¿¿ modulators	p. 97
2.3.4 Effect of the amplifier finite slew rate	p. 99
2.3.5 Effect of the switch finite on-resistance	p. 102
Effect on an ideal integrator	p. 102
Effect on the amplifier GB	p. 103
Effect on the amplifier SR	p. 105
2.4 Circuit Noise	p. 108
2.4.1 Noise in track-and-holds	p. 109
Track component	p. 110
Sampled-and-held component	p. 110
Folding-back effect	p. 111
2.4.2 Noise in SC integrators	p. 113
Switches controlled by ¿1	p. 114
Switches controlled by ¿2	p. 115
Opamp noise	p. 116
Noise in the references	p. 119
Total noise	p. 120
2.4.3 Circuit noise in ¿¿ modulators	p. 122
Fully-differential circuitry	p. 123
2.5 Clock Jitter	p. 124
2.6 Sources of Distortion	p. 125
2.6.1 Distortion due to the non-linear capacitors	p. 126
2.6.2 Distortion due to the amplifier non-linear gain	p. 130
2.6.3 Distortion due to the switch non-linear on-resistance	p. 133
2.6.4 Distortion due to the non-linear settling	p. 138
2.7 Summary	p. 139
Chapter 3 A Wideband ¿¿ Modulator in 3.3-V 0.35-¿m CMOS	p. 141
3.1 Design Methodology	p. 142
3.2 Topology Selection	p. 143
3.3 Switched-Capacitor Implementation	p. 151
3.4 Specifications for the Building Blocks	p. 153
3.4.1 Modulator sizing	p. 153
Fast modulator sizing	p. 153
Fine-tuning of blocks specs	p. 157
3.4.2 Integrator scaling	p. 159
3.5 Design of the Building Blocks	p. 160
3.5.1 Amplifiers	p. 160
Front-end amplifier	p. 162
Remaining amplifiers	p. 166
3.5.2 Comparators	p. 168
3.5.3 Switches	p. 169
3.5.4 Capacitors	p. 170
3.5.5 Programmable A/D/A converter	p. 173
A/D converter	p. 173
D/A converter	p. 174
Control circuitry	p. 175
3.5.6 Clock phase generator	p. 176
3.6 Layout and Prototyping	p. 177
3.7 Experimental Results	p. 179
3.7.1 Performance of the A/D/A converter	p. 182
3.7.2 Influence of jitter noise	p. 182
3.7.3 Influence of settling errors	p. 183
3.7.4 Influence of switching noise	p. 185
3.8 Performance Summary	p. 188
3.9 Performance Comparison with the State of the Art	p. 189
3.10 Summary	p. 192
Chapter 4 A ¿¿ Modulator in 2.5-V 0.25-¿m CMOS for ADSL/ADSL+	p. 193
4.1 Topology Selection	p. 195
4.2 Switched-Capacitor Implementation	p. 198
4.3 Specifications for the Building Blocks	p. 198
4.4 Design of the Building Blocks	p. 205
4.4.1 Amplifiers	p. 205
Front-end amplifiers	p. 205
Back-end amplifiers	p. 207
Non-linearities	p. 207
4.4.2 Comparators	p. 209
4.4.3 Switches	p. 210
4.4.4 Capacitors	p. 212
4.4.5 A/D/A converter	p. 212
A/D converter	p. 212
D/A converter	p. 214
4.4.6 Clock phase generator	p. 214
4.4.7 Auxiliary blocks	p. 215
Reference voltage generator	p. 215
Master current generator	p. 217
Anti-aliasing filter	p. 217
4.5 Layout and Prototyping	p. 217
4.6 Experimental Results	p. 219
4.7 Performance Summary	p. 223
4.8 Performance Comparison with the State of the Art	p. 225
4.9 Summary	p. 228
Chapter 5 A ¿¿ Modulator with Programmable Signal Gain for Automotive Sensor Interfaces	p. 229
5.1 Basic Design Considerations	p. 231
5.2 Architecture Selection and High-Level Sizing	p. 233
5.2.1 Modulator architecture	p. 235
5.2.2 SC implementation	p. 235
5.2.3 High-level sizing and building-block specifications	p. 239
5.3 Design of the Building Blocks	p. 239
5.3.1 Amplifiers	p. 239
5.3.2 Comparators	p. 243
5.3.3 Switches	p. 244
5.3.4 Capacitor arrays	p. 246
5.3.5 Auxiliary blocks	p. 246
5.4 Layout and Prototyping	p. 249
5.5 Experimental Results	p. 251
5.6 Summary	p. 256
Appendix A An Expandible Family of Cascade ¿¿ Modulators	p. 259
A.1 Topology Description	p. 259
A.2 Non-Ideal Performance	p. 263
Appendix B Power Estimator for Cascade ¿¿ Modulators	p. 267
B.1 Dominant Error Mechanisms	p. 267
B.2 Estimation of Power Consumption	p. 269
References	p. 275
Index	p. 293

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