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Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
|---|---|---|---|---|---|
Searching... | 30000010332586 | TK7874 H365 2012 | Open Access Book | Book | Searching... |
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Summary
Summary
The first encompassing treatise of this new and very important field puts the known physical limitations for classic 2D microelectronics
into perspective with the requirements for further microelectronics developments and market necessities. This two-volume handbook
presents 3D solutions to the feature density problem, addressing all important issues, such as wafer processing, die bonding, packaging
technology, and thermal aspects. It begins with an introductory part, which defines necessary goals, existing issues and relates 3D integration
to the semiconductor roadmap of the industry. Before going on to cover processing technology and 3D structure fabrication strategies in
detail. This is followed by fields of application and a look at the future of 3D integration.
The editors have assembled contributions from key academic and industrial players in the field, including Intel, Micron, IBM, Infineon,
Qimonda, NXP, Philips, Toshiba, Semitool, EVG, Tezzaron, Lincoln Labs, Fraunhofer, RPI, IMEC, CEA-LETI and many others.
Author Notes
Dr. Philip Garrou, from Microelectronic Consultants of North Carolina, specializes in thin film microelectronic materials and applications, prior to which he was Director of Technology and New Business Development for Dow Chemicals - Advanced Electronic Materials business. He
is a fellow of IEEE and IMAPS, has served as Associate Editor of the IEEE Transactions on Advanced Packaging, has authored two microelectronics texts and is co-author of over 75 peer reviewed publications and book chapters.
Dr. Christopher Bower is currently a Technical Manager at Semprius Inc., Durham, NC, where he leads a group working on the assembly and wafer-level packaging of advanced multi-junction solar cells for concentrator photovoltaics (CPV). Previously he was a senior scientist at RTI International where he worked on multiple DARPA-funded 3D integration programs. Dr. Bower has authored or co-authored over fifty papers and holds four patents.
Dr. Peter Ramm is head of the department Device and 3D Integration of Fraunhofer EMFT in Munich, Germany, where he is responsible for process integration of innovative devices and heterogeneous systems with a specific focus on 3D integration technologies. Dr. Ramm received the physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility where he was responsible for the process integration. In 1988 he joined Fraunhofer IFT in Munich, focusing for over two decades on 3D integration technologies. Peter Ramm is author or co-author of over 100 publications and 24 patents. He received
the 'Ashman Award 2009' from the International Electronics Packaging Society (IMAPS) 'For Pioneering Work on 3D IC Stacking and Integration, and leading-edge work on SiGe and Si technologies'. Peter Ramm is Fellow and Life Member of IMAPS, organizing committee
and founding member of IEEE 3DIC conference and co-editor of Wiley's 'Handbook of Wafer Bonding'.
Table of Contents
| 1 Introduction to 3D Integration |
| 2 Drivers for 3D Integration |
| 3 Overview of 3D Process Technology |
| Part I Through Silicon Via Fabrication |
| 4 Deep Reactive Ion Etching |
| 5 Laser Ablation |
| 6 Insulation - SiO2 |
| 7 Insulation - Organic Dielectrics |
| 8 Copper Plating |
| 9 Metallization by chemical vapor deposition of W and Cu |
| Part II Wafer Thinning and Bonding Technology |
| 10 Fabrication, Processing and Singulation of Thin Wafers |
| 11 Overview of Bonding Technologies for 3D Integration |
| 12 Chip-to-Wafer and Wafer-to-Wafer Integration Schemes |
| 13 Polymer Adhesive Bonding Technology |
| 14 Bonding with Intermetallic Compounds |
| Part III Integration Processes |
| 15 Commercial Activity |
| 16 Fraunhofer IZM |
| 17 Interconnect Process at the University of Arkansas |
| 18 Vertical Interconnection by ASET at Toshiba |
| 19 3D Integration at CEA-LETI |
| 20 Lincoln Laboratory's Integration Technology |
| 21 3D Integration Technologies at IMEC |
| 22 Fabrication Using Copper Thermo-Compression Bonding at MIT |
| 23 Rensselaer 3D Integration Processes |
| 24 3D Integration at Tezzaron Semiconductor Corporation |
| 25 3D Integration at Ziptronix, Inc |
| 26 3D Integration at ZyCube Sendai Lab. |
| Part IV Design, Performance, and Thermal Management |
| 27 Design for 3D Integration at NC State University |
| 28 Design for 3D Integration at Fraunhofer IIS-EAS |
| 29 Multiproject Circuit Design and Layout in Lincoln Laboratory's 3D Technology |
| 30 Computer-aided Design for 3D Circuits at the University of Minnesota |
| 31 Electrical Performance of 3D Circuits |
| 32 Testing of 3D Circuits |
| 33 Thermal Management of Vertically Integrated Packages at IBM Zurich |
| Part V Applications |
| 34 3D and Microprocessors |
| 35 3D Memories |
| 36 Sensor Arrays |
| 37 Power Devices |
| 38 Wireless Sensor Systems - The e-CUBES Project |
| 39 Conclusions |
