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Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
|---|---|---|---|---|---|
Searching... | 30000010113076 | TK7887.6 D67 2006 | Open Access Book | Book | Searching... |
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Summary
Summary
IGH-SPEED Digital to Analog (D/A) converters are essential components in digi- Htal communication systems providing the necessary conversion of signals encoding information in bits to signals encoding information in their amplitude vs. time domain characteristics. In general, they are parts of a larger system, the interface, which c- sists of several signal conditioning circuits. Dependent on where the converter is located within the chain of circuits in the interface, signal processing operations are partitioned in those realized with digital techniques, and those with analog. The rapid evolution of CMOS technology has established implicit and explicite trends related to the interface, and in particular to the D/A converter. The implicit relationship comes via the growth of digital systems. First, it is a global trend with respect to all interface circuits that increasing operating frequencies of digital systems place a similar demand for the interface circuits. The second trend takes place locally within the int- face. Initially, the D/A converter was placed at the beginning of the interface chain, and all signal conditioning was implemented in the analog domain after the D/A conversion. The increasing ?exibility and robustness of digital signal processing shifted the D/A converter closer to the end point of the chain where the demands for high quality high frequency operation are very high.
Author Notes
Dr Konstantinos Doris is from Philips Research Laboratories in Eindhoven. His advisor, Prof. Arthur van Roermund, finds his work in the subject of high-speed DA converters an excellent candidate for us to publish.
Dr. Leenaerts is seen to be one of the top experts in RF Circuit Design in Europe.
Table of Contents
| Glossary |
| Abbreviations |
| Preface |
| 1 Digital to Analog conversion concepts |
| 1.1 Functional aspects |
| 1.2 Algorithmic aspects |
| 1.3 Signal processing aspects |
| 1.4 Circuit aspects |
| 1.5 Conclusions |
| 2 Framework for Analysis and Synthesis of DACs |
| 2.1 Overview |
| 2.2 Framework description |
| 3 Current Steering DACs |
| 3.1 Basic circuit |
| 3.2 Implementations and technology impact |
| 4 Dynamic limitations of Current Steering DACs |
| 4.1 State of the art in dynamic linearity |
| 4.2 Dynamic limitations of current steering DACs |
| 4.3 Conclusions |
| 5 Current Steering DAC circuit error analysis |
| 5.1 Amplitude domain errors |
| 5.2 Time domain errors |
| 5.3 Conclusions |
| 6 High-level modeling of Current Steering DACs |
| 6.1 System modeling |
| 6.2 Error properties and classification |
| 6.3 Functional error generation mechanisms |
| 6.4 Conclusions |
| 7 Functional modeling of timing errors |
| 7.1 Non-uniform timing |
| 7.2 Stochastic non-uniform timing analysis |
| 7.3 Deterministic non-uniform timing |
| 7.4 Conclusions |
| 8 Functional analysis of local timing errors |
| 8.1 Local timing error analysis |
| 8.2 High level architectural parameter tradeoffs: segmentation |
| 8.3 Conclusions |
| 9 Circuit analysis of local timing errors |
| 9.1 Circuit analysis with linear models |
| 9.2 Local timing error tradeoffs |
| 9.3 Conclusions |
| 10 Synthesis concepts for CS DACs |
| 10.1 Information management in the CS DAC |
| 10.2 Synthesis Policy |
| 10.3 A-posteriori error correction methods |
| 10.4 Conclusions |
| 11 Design of a 12 bit 500 Msample/s DAC |
| 11.1 Design approach |
| 11.2 Architecture |
| 11.3 Switched-Current cell |
| 11.4 Decoder, data synchronization and conditioning |
| 11.5 Layout |
| 11.6 Experimental results |
| 11.7 Conclusions |
| References |
| A Output spectrum for timing errors |
| A.1 Power spectrum of y(t) for random timing errors |
| A.2 Spectrum of y(t) for deterministic timing errors |
| B Literature data |
