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Summary
Summary
A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits. The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology, and potential problems with each type of circuit.
Many design examples are used throughout, most of which have been tested with silicon implementation or employed in real-world products. This ensures that the material presented relevant to both students studying the topic as well as readers requiring a practical viewpoint.
Covers CMOS voltage reference circuit design, from the basics through to advanced topics Provides an overview of basic device physics and different building blocks of voltage reference designs Features real-world examples based on actual silicon implementation Includes analytical exercises, simulation exercises, and silicon layout exercises, giving readers guidance and design layout experience for voltage reference circuits Solution manual available to instructors from the book's companion websiteThis book is highly useful for graduate students in VLSI design, as well as practicing analog engineers and IC design professionals. Advanced undergraduates preparing for further study in VLSI will also find this book a helpful companion text.
Author Notes
Chi-Wah Kok, Canaan Microelectronics Corporation Limited, China
Chi-Wah Kok obtained his degree from the University of Wisconsin Madison. Since 1992, he has been working with various semi-conductor companies, research institutions and universities, which include AT&T Labs Research, Holmdel, SONY U.S. Research Labs, Stanford University, Hong Kong University of Science and Technology, Hong Kong Polytechnic University, City University of Hong Kong, and Lattice Semiconductor. In 2006, he founded Canaan Microelectronics Corp Ltd., a fabless IC company with products in mixed signal IC for consumer electronics. He has extensively applied signal processing techniques to improve the circuit topologies, designs, and fabrication technologies within Canaan. This includes the application of semidefinite programming to circuit design optimization, abstract algebra in switched capacitor circuit topologies improvement, and nonlinear optimization methods to optimize high voltage MOSFET layout and fabrication.
Wing-Shan Tam, Canaan Microelectronics Corp Limited, China
Wing-Shan Tam received her BEng degree in electronic engineering from The Chinese University of Hong Kong, and MSc degree in electronic and information engineering from The Hong Kong Polytechnic University, and PhD degree in electronic engineering from the City University of Hong Kong in 2004, 2007, and 2010, respectively. Currently, she is the Engineering Manager of Canaan Microelectronics Corp Ltd., and she has been working with CMOS circuit design since 2004. Her research interests include mixed-signal integrated circuit design for data conversion and power-management.
Table of Contents
About the Authors | p. ix |
Preface | p. xi |
Acknowledgements | p. xiii |
Nomenclature | p. xv |
1 Warm Up | p. 1 |
1.1 Bipolar Junction Transistors | p. 2 |
1.1.1 Differential V BE | p. 5 |
1.2 Metal-Oxide Semiconductor Field-Effect Transistor | p. 7 |
1.2.1 Cutoff Region | p. 11 |
1.2.2 Subthreshold Conduction | p. 11 |
1.2.3 Triode Region | p. 14 |
1.2.4 Saturation Region | p. 16 |
1.2.5 Thermal Properties | p. 19 |
1.2.6 Channel Length Modulation Effect | p. 23 |
1.3 Diode | p. 23 |
1.4 Resistor | p. 25 |
1.4.1 Dummy Element | p. 27 |
1.4.2 Guard Ring | p. 27 |
1.4.3 Sheet Resistance | p. 27 |
1.5 Device Matching | p. 28 |
1.5.1 Application of Statistics to Circuit Design | p. 28 |
1.5.2 Systematic Variation | p. 30 |
1.6 Simulation Models for Circuit Design | p. 31 |
1.6.1 Process Variation and Typical Design | p. 32 |
1.6.2 Process Corners | p. 34 |
1.7 Noise | p. 36 |
1.7.1 Types of Noises | p. 36 |
1.7.2 Sums and Multiplications of Noises | p. 38 |
1.8 Fabrication Technology | p. 39 |
1.9 Book Organization | p. 40 |
1.10 Exercises | p. 42 |
References | p. 46 |
2 Voltage Reference | p. 49 |
2.1 Performance Measures | p. 49 |
2.1.1 Line Regulation | p. 51 |
2.1.2 Temperature Coefficient | p. 54 |
2.1.3 Power Supply Rejection Ratio | p. 56 |
2.1.4 Quiescent Current | p. 59 |
2.1.5 Output Noise | p. 60 |
2.2 Other Design Considerations | p. 62 |
2.3 Summary | p. 63 |
2.4 Exercises | p. 65 |
References | p. 70 |
3 Bandgap Voltage Reference | p. 71 |
3.1 Widlar Bandgap Voltage Reference Circuit | p. 71 |
3.2 Drain Voltage Equalization Current Mirror | p. 74 |
3.2.1 Opamp Based ß-Multiplier Bandgap Voltage Reference Circuit | p. 76 |
3.2.2 Bandgap Voltage Reference Circuit | p. 77 |
3.3 Major Circuit Elements | p. 81 |
3.3.1 Operational Amplifier | p. 81 |
3.3.2 Current Mirror | p. 86 |
3.3.3 Startup Circuit | p. 88 |
3.3.4 Resistor Network | p. 93 |
3.3.5 Bipolar Transistor | p. 94 |
3.4 Complete Layout | p. 95 |
3.5 Summary | p. 95 |
3.6 Exercises | p. 96 |
References | p. 101 |
4 Error Sources in Bandgap Voltage Reference Circuit | p. 103 |
4.1 Non-Ideal Opamp | p. 103 |
4.1.1 Input Offset Voltage | p. 104 |
4.1.2 Limited Gain and Power Supply Rejection Ratio | p. 112 |
4.1.3 Noise | p. 113 |
4.2 Current Mirror Mismatch | p. 114 |
4.2.1 Channel Length Modulation Effect Compensation | p. 116 |
4.2.2 Cascode Current Mirror | p. 117 |
4.3 Bipolar Transistor | p. 122 |
4.3.1 Size Variation | p. 122 |
4.3.2 Series Base Resistance | p. 122 |
4.3.3 ß Variation | p. 125 |
4.4 Resistor Variation | p. 126 |
4.5 Power Supply Variation | p. 127 |
4.5.1 Pre-Regulation | p. 132 |
4.6 Output Loading | p. 135 |
4.7 Output Noise | p. 138 |
4.8 Voltage Reference Circuit Trimming | p. 140 |
4.8.1 Linked Fuse Resistor Trimming | p. 141 |
4.8.2 Resistor Trimming Circuit Analysis | p. 142 |
4.8.3 Modulated Trimming | p. 146 |
4.8.4 Voltage Domain Trimming | p. 148 |
4.8.5 Current Domain Trimming | p. 149 |
4.9 Summary | p. 149 |
4.10 Exercises | p. 151 |
References | p. 161 |
Advanced Voltage Reference Circuits | |
5 Temperature Compensation Techniques | p. 165 |
5.1 V BE - ¿ V BE Compensation | p. 166 |
5.1.1 Brokaw Bandgap Voltage Reference | p. 168 |
5.1.2 ß-Multiplier V BE - ¿V BE Compensation | p. 170 |
5.2 Widlar PTAT Current Source and V BE Compensation | p. 175 |
5.3 V GS Based Temperature Compensation | p. 177 |
5.3.1 V GS Current Source | p. 178 |
5.4 Summary | p. 182 |
5.5 Exercises | p. 183 |
References | p. 189 |
6 Sub-1V Voltage Reference Circuit | p. 191 |
6.1 Sub-1V Output Stage | p. 193 |
6.2 Voltage Headroom in Opamp based ß-multiplier Voltage Reference Circuit | p. 195 |
6.2.1 Opamp with NMOS Input Stage | p. 197 |
6.2.2 Local Voltage Boosting | p. 198 |
6.2.3 Low V th Transistor | p. 198 |
6.2.4 Bulk-Driven Transistors | p. 199 |
6.3 Sub-1V Bandgap Voltage Reference by Resistive Division | p. 199 |
6.3.1 Resistive Divided V BE | p. 202 |
6.3.2 Independent Biased Resistive Divided V BE | p. 206 |
6.4 Peaking Current Source and V BE Compensation | p. 209 |
6.5 Weighted ¿ V GS Compensation | p. 211 |
6.6 Summary | p. 214 |
6.7 Exercises | p. 215 |
References | p. 222 |
7 High Order Curvature Correction | p. 223 |
7.1 Compensation Order | p. 224 |
7.2 Second Order Temperature Compensation | p. 228 |
7.2.1 Second Order Current Source | p. 229 |
7.2.2 Current Subtraction | p. 232 |
7.2.3 Current Addition | p. 236 |
7.3 BJT Current Subtraction | p. 238 |
7.4 Piecewise Linear Compensation | p. 240 |
7.5 Sum and Difference of Sources with Similar Temperature Dependence | p. 243 |
7.5.1 Difference of Voltages with Similar Temperature Dependence | p. 244 |
7.5.2 Sum of Voltages with Inverted Temperature Dependence | p. 245 |
7.5.3 Multi-threshold Voltages Curvature Compensated Voltage Reference | p. 247 |
7.6 Summary | p. 252 |
7.7 Exercises | p. 253 |
References | p. 257 |
8 CMOS Voltage Reference without Resistors | p. 259 |
8.1 Generation of Weighted PTAT Source By Inverse Functions | p. 260 |
8.1.1 Weighted Differential Circuit | p. 260 |
8.1.2 Negative Impedance Converter | p. 262 |
8.2 Resistorless Voltage and Current Sources | p. 265 |
8.2.1 Resistorless Voltage Source | p. 265 |
8.2.2 Resistorless Current Source | p. 266 |
8.3 First Order Compensated Resistorless Bandgap Voltage Reference Circuit | p. 268 |
8.3.1 Voltage Summation Based Resistorless Reference Circuit | p. 269 |
8.3.2 Current Summation Based Resistorless Reference Circuit | p. 270 |
8.4 Resistorless Sub-Bandgap Reference Circuit | p. 270 |
8.4.1 The Voltage Summation Approach | p. 271 |
8.4.2 CTAT Voltage Reduction | p. 273 |
8.5 Summary | p. 279 |
8.6 Exercises | p. 280 |
References | p. 281 |
A SPICE Model File | p. 283 |
B SPICE Netlist of Voltage Reference Circuit | p. 287 |
Index | p. 289 |