Digital computer arithmetic datapath design using verilog hdl

The role of arithmetic in datapath design in VLSI design has been increasing in importance over the last several years due to the demand for processors that are smaller, faster, and dissipate less power. Unfortunately, this means that many of these datapaths will be complex both algorithmically and circuit wise. As the complexity of the chips increases, less importance will be placed on understanding how a particular arithmetic datapath design is implemented and more importance will be given to when a product will be placed on the market. This is because many tools that are available today, are automated to help the digital system designer maximize their efficiently. Unfortunately, this may lead to problems when implementing particular datapaths. The design of high-performance architectures is becoming more compli cated because the level of integration that is capable for many of these chips is in the billions. Many engineers rely heavily on software tools to optimize their work, therefore, as designs are getting more complex less understanding is going into a particular implementation because it can be generated automati cally. Although software tools are a highly valuable asset to designer, the value of these tools does not diminish the importance of understanding datapath ele ments. Therefore, a digital system designer should be aware of how algorithms can be implemented for datapath elements. Unfortunately, due to the complex ity of some of these algorithms, it is sometimes difficult to understand how a particular algorithm is implemented without seeing the actual code.

Preface	p. ix
1. Motivation	p. 1
1.1 Why Use Verilog HDL?	p. 1
1.2 What this book is not : Main Objective	p. 2
1.3 Datapath Design	p. 3
2. Verilog at the Rtl Level	p. 7
2.1 Abstraction	p. 7
2.2 Naming Methodology	p. 10
2.2.1 Gate Instances	p. 11
2.2.2 Nets	p. 12
2.2.3 Registers	p. 12
2.2.4 Connection Rules	p. 13
2.2.5 Vectors	p. 14
2.2.6 Memory	p. 14
2.2.7 Nested Modules	p. 15
2.3 Force Feeding Verilog : the Test Bench	p. 16
2.3.1 Test Benches	p. 18
2.4 Other Odds and Ends within Verilog	p. 19
2.4.1 Concatenation	p. 19
2.4.2 Replication	p. 21
2.4.3 Writing to Standard Output	p. 21
2.4.4 Stopping a Simulation	p. 21
2.5 Timing: For Whom the Bell Tolls	p. 22
2.5.1 Delay-based Timing	p. 22
2.5.2 Event-Based Timing	p. 23
2.6 Synopsys Design Ware Intellectual Property (IP)	p. 24
2.7 Verilog 2001	p. 24
2.8 Summary	p. 26
3. Addition	p. 27
3.1 Half Adders	p. 28
3.2 Full Adders	p. 28
3.3 Ripple Carry Adders	p. 30
3.4 Ripple Carry Adder/Subtractor	p. 31
3.4.1 Carry Lookahead Adders	p. 34
3.4.1.1 Block Carry Lookahead Generators	p. 36
3.5 Carry Skip Adders	p. 40
3.5.1 Optimizing the Block Size to Reduce Delay	p. 42
3.6 Carry Select Adders	p. 43
3.6.1 Optimizing the Block Size to Reduce Delay	p. 46
3.7 Prefix Addition	p. 47
3.8 Summary	p. 52
4. Multiplication	p. 55
4.1 Unsigned Binary Multiplication	p. 56
4.2 Carry-Save Concept	p. 56
4.3 Carry-Save Array Multipliers (CSAM)	p. 60
4.4 Tree Multipliers	p. 61
4.4.1 Wallace Tree Multipliers	p. 61
4.4.2 Dadda Tree Multipliers	p. 65
4.4.3 Reduced Area (RA) Multipliers	p. 68
4.5 Truncated Multiplication	p. 71
4.6 Two's Complement Multiplication	p. 78
4.7 Signed-Digit Numbers	p. 82
4.8 Booth's algorithm	p. 86
4.8.1 Bitwise Operators	p. 87
4.9 Radix-4 Modified Booth Multipliers	p. 89
4.9.1 Signed Radix-4 Modified Booth Multiplication	p. 91
4.10 Fractional Multiplication	p. 92
4.11 Summary	p. 93
5. Division Using Recurrence	p. 103
5.1 Digit Recurrence	p. 104
5.2 Quotient Digit Selection	p. 105
5.2.1 Containment Condition	p. 106
5.2.2 Continuity Condition	p. 106
5.3 On-the-Fly-Conversion	p. 108
5.4 Radix 2 Division	p. 112
5.5 Radix 4 Division with [alpha] = 2 and Non-redundant Residual	p. 115
5.5.1 Redundant Adder	p. 118
5.6 Radix 4 Division with [alpha] = 2 and Carry-Save Adder	p. 119
5.7 Radix 16 Division with Two Radix 4 Overlapped Stages	p. 122
5.8 Summary	p. 126
6. Elementary Functions	p. 129
6.1 Generic Table Lookup	p. 131
6.2 Constant Approximations	p. 133
6.3 Piecewise Constant Approximation	p. 134
6.4 Linear Approximations	p. 136
6.4.1 Round to Nearest Even	p. 138
6.5 Bipartite Table Methods	p. 141
6.5.1 SBTM and STAM	p. 142
6.6 Shift and Add: CORDIC	p. 147
6.7 Summary	p. 152
7. Division Using Multiplicative-Based Methods	p. 161
7.1 Newton-Raphson Method for Reciprocal Approximation	p. 161
7.2 Multiplicative-Divide Using Convergence	p. 166
7.3 Summary	p. 168
References	p. 171
Index	p. 179

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