ESD : RF technology and circuits

Title:

Personal Author:

Voldman, Steven Howard

Publication Information:

Hoboken, NJ : John Wiley & Sons, 2006

ISBN:

9780470847558

Subject Term:

Radio frequency integrated circuits -- Design and construction

Radio frequency integrated circuits -- Protection

Electrostatics

Electric discharges -- Prevention

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With the growth of high-speed telecommunications and wireless technology, it is becoming increasingly important for engineers to understand radio frequency (RF) applications and their sensitivity to electrostatic discharge (ESD) phenomena. This enables the development of ESD design methods for RF technology, leading to increased protection against electrical overstress (EOS) and ESD.

ESD: RF Technology and Circuits:

Presents methods for co-synthesizisng ESD networks for RF applications to achieve improved performance and ESD protection of semiconductor chips; discusses RF ESD design methods of capacitance load transformation, matching network co-synthesis, capacitance shunts, inductive shunts, impedance isolation, load cancellation methods, distributed loads, emitter degeneration, buffering and ballasting; examines ESD protection and design of active and passive elements in RF complementary metal-oxide-semiconductor (CMOS), RF laterally-diffused metal oxide semiconductor (LDMOS), RF BiCMOS Silicon Germanium (SiGe), RF BiCMOS Silicon Germanium Carbon (SiGeC), and Gallim Arsenide technology; gives information on RF ESD testing methodologies, RF degradation effects, and failure mechanisms for devices, circuits and systems; highlights RF ESD mixed-signal design integration of digital, analog and RF circuitry; sets out examples of RF ESD design computer aided design methodologies; covers state-of-the-art RF ESD input circuits, as well as voltage-triggered to RC-triggered ESD power clamps networks in RF technologies, as well as off-chip protection concepts.

Following the authors series of books on ESD, this book will be a thorough overview of ESD in RF technology for RF semiconductor chip and ESD engineers. Device and circuit engineers working in the RF domain, and quality, reliability and failure analysis engineers will also find it a valuable reference in the rapidly growing are of RF ESD design. In addition, it will appeal to graduate students in RF microwave technology and RF circuit design.

Author Notes

Steven H. Voldman is the author of ESD: RF Technology and Circuits, published by Wiley.

Preface	p. xv
Acknowledgements	p. xxi
Chapter 1 RF Design and ESD	p. 1
1.1 Fundamental Concepts of ESD Design	p. 1
1.2 Fundamental Concepts of RF ESD Design	p. 4
1.3 Key RF ESD Contributions	p. 10
1.4 Key RF ESD Patents	p. 13
1.5 ESD Failure Mechanisms	p. 13
1.5.1 RF CMOS ESD Failure Mechanisms	p. 14
1.5.2 Silicon Germanium ESD Failure Mechanisms	p. 15
1.5.3 Silicon Germanium Carbon ESD Failure Mechanisms in Silicon Germanium Carbon Devices	p. 15
1.5.4 Gallium Arsenide Technology ESD Failure Mechanisms	p. 16
1.5.5 Indium Gallium Arsenide ESD Failure Mechanisms	p. 16
1.5.6 RF Bipolar Circuits ESD Failure Mechanisms	p. 17
1.6 RF Basics	p. 17
1.7 Two-Port Network Parameters	p. 21
1.7.1 Z-Parameters	p. 21
1.7.2 Y-Parameters	p. 22
1.7.3 S-Parameters	p. 22
1.7.4 T-Parameters	p. 23
1.8 Stability: RF Design Stability and ESD	p. 24
1.9 Device Degradation and ESD Failure	p. 26
1.9.1 ESD-Induced D.C. Parameter Shift and Failure Criteria	p. 26
1.9.2 RF Parameters, ESD Degradation, and Failure Criteria	p. 28
1.10 RF ESD Testing	p. 29
1.10.1 ESD Testing Models	p. 29
1.10.2 RF Maximum Power-to-Failure and ESD Pulse Testing Methodology	p. 33
1.10.3 ESD-Induced RF Degradation and S-Parameter Evaluation Test Methodology	p. 37
1.11 Time Domain Reflectometry (TDR) and Impedance Methodology for ESD Testing	p. 39
1.11.1 Time Domain Reflectometry (TDR) ESD Test System Evaluation	p. 40
1.11.2 ESD Degradation System Level Method - Eye Tests	p. 44
1.12 Product Level ESD Test and RE Functional Parameter Failure	p. 46
1.13 Combined RF and ESD TLP Test Systems	p. 48
1.14 Closing Comments and Summary	p. 51
Problems	p. 52
References	p. 53
Chapter 2 RF ESD Design	p. 61
2.1 ESD Design Methods: Ideal ESD Networks and RF ESD Design Windows	p. 61
2.1.1 Ideal ESD Networks and the Current-Voltage d.c. Design Window	p. 61
2.1.2 Ideal ESD Networks in the Frequency Domain Design Window	p. 63
2.2 RF ESD Design Methods: Linearity	p. 64
2.3 RF ESD Design: Passive Element Quality Factors and Figures of Merit	p. 68
2.4 RF ESD Design Methods: Method of Substitution	p. 70
2.4.1 Method of Substitution of Passive Element to ESD Network Element	p. 71
2.4.2 Substitution of ESD Network Element to Passive Element	p. 72
2.5 RF ESD Design Methods: Matching Networks and RF ESD Networks	p. 73
2.5.1 RF ESD Method - Conversion of Matching Networks to ESD Networks	p. 74
2.5.2 RF ESD Method: Conversion of ESD Networks into Matching Networks	p. 76
2.5.2.1 Conversion of ESD Networks into L-Match Networks	p. 76
2.5.2.2 Conversion of ESD Networks into [Pi]-Match Networks	p. 77
2.5.2.3 Conversion of ESD Networks into T-Match Networks	p. 78
2.6 RF ESD Design Methods: Inductive Shunt	p. 79
2.7 RF ESD Design Methods: Cancellation Method	p. 82
2.7.1 Quality Factors and the Cancellation Method	p. 82
2.7.2 Inductive Cancellation of Capacitance Load and Figures of Merit	p. 83
2.7.3 Cancellation Method and ESD Circuitry	p. 85
2.8 RF ESD Design Methods: Impedance Isolation Technique Using LC Resonator	p. 89
2.9 RF ESD Design Methods: Lumped versus Distributed Loads	p. 91
2.9.1 RF ESD Distributed Load with Coplanar Wave Guides	p. 92
2.9.2 RF ESD Distribution Coplanar Waveguides Analysis Using ABCD Matrices	p. 93
2.10 ESD RF Design Synthesis and Floor Planning: RF, Analog, and Digital Integration	p. 95
2.10.1 ESD Power Clamp Placement Within a Domain	p. 96
2.10.2 Power Bus Architecture and ESD Design Synthesis	p. 97
2.10.3 V[subscript DD]-to-V[subscript SS] Power Rail Protection	p. 98
2.10.4 VoD-to-Analog Vdd and Vdo-Io-RF Vcc Power Rail Protection	p. 99
2.10.5 Interdomain BSD Protection Networks	p. 100
2.11 ESD Circuits and RF Bond Pad Integration	p. 101
2.12 ESD Structures Under Wire Bond Pads	p. 103
2.13 Summary and Closing Comments	p. 106
Problems	p. 106
References	p. 108
Chapter 3 RF CMOS and ESD	p. 111
3.1 RF CMOS: ESD Device Comparisons	p. 111
3.2 Circular RF ESD Devices	p. 116
3.3 RF ESD Design-ESD Wiring Design	p. 118
3.4 RF Passives: ESD and Schottky Barrier Diodes	p. 120
3.5 RF Passives: ESD and Inductors	p. 122
3.6 RF Passives: ESD and Capacitors	p. 127
3.6.1 Metal-oxide-Semiconductor and Metal-Insulator-Metal Capacitors	p. 128
3.6.2 Varactors and Hyper-Abrupt Junction Varactor Capacitors	p. 128
3.6.3 Metal-ILD-Metal Capacitors	p. 129
3.6.4 Vertical Parallel Plate (VPP) Capacitors	p. 130
3.7 Summary and Closing Comments	p. 131
Problems	p. 132
References	p. 133
Chapter 4 RF CMOS ESD Networks	p. 139
4.1 RF CMOS Input Circuits	p. 139
4.1.1 RF CMOS ESD Diode Networks	p. 139
4.1.2 RF CMOS Diode String ESD Network	p. 143
4.2 RF CMOS: Diode-Inductor ESD Networks	p. 145
4.2.1 RF Inductor-Diode ESD Networks	p. 147
4.2.2 RF Diode-Inductor ESD Networks	p. 148
4.3 RF CMOS Impedance Isolation LC Resonator ESD Networks	p. 149
4.3.1 RF CMOS LC-Diode ESD Networks	p. 150
4.3.2 RF CMOS Diode-LC ESD Networks	p. 150
4.3.3 Experimental Results of the RF CMOS LC-Diode Networks	p. 151
4.4 RF CMOS LNA ESD Design	p. 152
4.4.1 RF LNA ESD Design: Low Resistance ESD Inductor and ESD Diode Clamping Elements in [Pi]-Configuration	p. 153
4.5 RF CMOS T-Coil Inductor ESD Input Network	p. 157
4.6 RF CMOS Distributed ESD Networks	p. 159
4.6.1 RF CMOS Distributed RF ESD Networks	p. 159
4.6.2 RF CMOS Distributed RF ESD Networks using Series Inductor and Dual-Diode Shunt	p. 160
4.6.3 RF CMOS Distributed RF ESD Networks using Series Inductor and MOSFET Parallel Shunt	p. 163
4.7 RF CMOS Distributed ESD Networks: Transmission Lines and Coplanar Waveguides	p. 165
4.8 RF CMOS: ESD and RF LDMOS Power Technology	p. 167
4.9 RF CMOS ESD Power Clamps	p. 170
4.9.1 RC-Triggered MOSFET ESD Power Clamp	p. 172
4.9.2 High Voltage RC-Triggered MOSFET ESD Power Clamp	p. 174
4.9.3 Voltage-Triggered MOSFET ESD Power Clamps	p. 175
4.10 Summary and Closing Comments	p. 176
Problems	p. 177
References	p. 178
Chapter 5 Bipolar Physics	p. 183
5.1 Bipolar Device Physics	p. 183
5.1.1 Bipolar Transistor Current Equations	p. 183
5.1.2 Bipolar Current Gain and Collector-to-Emitter Transport	p. 184
5.1.3 Unity Current Gain Cutoff Frequency	p. 185
5.1.4 Unity Power Gain Cutoff Frequency	p. 186
5.2 Transistor Breakdown	p. 186
5.2.1 Avalanche Multiplication and Breakdown	p. 186
5.2.2 Bipolar Transistor Breakdown	p. 188
5.3 Kirk Effect	p. 190
5.4 Johnson Limit: Physical Limitations of the Transistor	p. 191
5.4.1 Voltage-Frequency Relationship	p. 191
5.4.2 Johnson Limit Current-Frequency Formulation	p. 193
5.4.3 Johnson Limit Power Formulation	p. 194
5.5 RF Instability: Emitter Collapse	p. 195
5.6 ESD RF Design Layout: Emitter, Base, and Collector Configurations	p. 201
5.7 ESD RF Design Layout: Utilization of a Second Emitter (Phantom Emitter)	p. 204
5.8 ESD RF Design Layout: Emitter Ballasting	p. 208
5.9 ESD RF Design Layout: Thermal Shunts and Thermal Lenses	p. 210
5.10 Base-Ballasting and RF Stability	p. 211
5.11 Summary and Closing Comments	p. 213
Problems	p. 213
References	p. 214
Chapter 6 Silicon Germanium and ESD	p. 217
6.1 Heterojunctions and Silicon Germanium Technology	p. 217
6.1.1 Silicon Germanium HBT Devices	p. 218
6.1.2 Silicon Germanium Device Structure	p. 219
6.2 Silicon Germanium Physics	p. 221
6.3 Silicon Germanium Carbon	p. 224
6.4 Silicon Germanium ESD Measurements	p. 226
6.4.1 Silicon Germanium Collector-to-Emitter ESD Stress	p. 227
6.4.2 ESD Comparison of Silicon Germanium HBT and Silicon BJT	p. 229
6.4.3 SiGe HBT Electrothermal Human Body Model (HBM) Simulation of Collector-Emitter Stress	p. 232
6.5 Silicon Germanium Carbon Collector-Emitter ESD Measurements	p. 233
6.6 Silicon Germanium Transistor Emitter-Base Design	p. 237
6.6.1 Epitaxial-Base Heterojunction Bipolar Transistor (HBT) Emitter-Base Design	p. 238
6.6.2 Emitter-Base Design RF Frequency Performance Metrics	p. 240
6.6.3 SiGe HBT Emitter-Base Resistance Model	p. 240
6.6.4 SiGe HBT Emitter-Base Design and Silicide Placement	p. 241
6.6.5 Self-Aligned (SA) Emitter-Base Design	p. 245
6.6.6 Non-self aligned (NSA) Emitter-Base Design	p. 248
6.6.6.1 NSA Human Body Model (HBM) Step Stress	p. 249
6.6.6.2 Transmission Line Pulse (TLP) Step Stress	p. 250
6.6.6.3 RF Testing of SiGe HBT Emitter-Base Configuration	p. 251
6.6.6.4 Unity Current Gain Cutoff Frequency-Collector Current Plots	p. 254
6.6.7 Silicon Germanium Carbon - ESD-Induced S-Parameter Degradation	p. 256
6.6.8 Electrothermal Simulation of Emitter-Base Stress	p. 258
6.7 Field-Oxide (FOX) Isolation Defined Silicon Germanium Heterojunction Bipolar Transistor HBM Data	p. 259
6.8 Silicon Germanium HBT Multiple-Emitter Study	p. 260
6.9 Summary and Closing Comments	p. 262
Problems	p. 262
References	p. 263
Chapter 7 Gallium Arsenide and ESD	p. 269
7.1 Gallium Arsenide Technology and ESD	p. 269
7.2 Gallium Arsenide Energy-to-Failure and Power-to-Failure	p. 269
7.3 Gallium Arsenide ESD Failures in Active and Passive Elements	p. 272
7.4 Gallium Arsenide HBT Devices and ESD	p. 273
7.4.1 Gallium Arsenide HBT Device ESD Results	p. 274
7.4.2 Gallium Arsenide HBT Diode Strings	p. 275
7.5 Gallium Arsenide HBT-Based Passive Elements	p. 277
7.5.1 GaAs HBT Base-Collector Varactor	p. 277
7.6 Gallium Arsenide Technology Table of Failure Mechanisms	p. 279
7.7 Indium Gallium Arsenide and ESD	p. 279
7.8 Indium Phosphide (InP) and ESD	p. 281
7.9 Summary and Closing Comments	p. 281
Problems	p. 281
References	p. 282
Chapter 8 Bipolar Receiver Circuits and Bipolar ESD Networks	p. 287
8.1 Bipolar Receivers and ESD	p. 287
8.2 Single Ended Common-Emitter Receiver Circuits	p. 288
8.2.1 Single-Ended Bipolar Receiver with D.C. Blocking Capacitors	p. 289
8.2.2 Single-Ended Bipolar Receiver with D.C. Blocking Capacitors and ESD Protection	p. 290
8.2.3 Bipolar Single-Ended Common-Emitter Receiver Circuit with Feedback Circuit	p. 291
8.2.3.1 Bipolar Single-Ended Common-Emitter Circuit with Resistor Feedback Element	p. 291
8.2.3.2 Bipolar Single-Ended Common-Emitter Receiver Circuit with Resistor-Capacitor Feedback Element	p. 292
8.2.4 Bipolar Single-Ended Common-Emitter Receiver Circuit with Emitter Degeneration	p. 293
8.2.5 Bipolar Single-Ended Common Emitter Circuit with Balun Output	p. 297
8.2.6 Bipolar Single-Ended Series Cascode Receiver Circuits	p. 298
8.3 Bipolar Differential Receiver Circuits	p. 300
8.3.1 Bipolar Differential Cascode Common-Emitter Receiver Circuits	p. 302
8.4 Bipolar ESD Input Circuits	p. 303
8.4.1 Diode-Configured Bipolar ESD Input Circuits	p. 307
8.4.2 Bipolar ESD Input: Resistor Grounded Base Bipolar ESD Input	p. 308
8.5 Bipolar-Based ESD Power Clamps	p. 312
8.5.1 Bipolar Voltage-Triggered ESD Power Clamps	p. 312
8.5.2 Zener Breakdown Voltage-Triggered ESD Power Clamps	p. 312
8.5.3 BV[subscript CEO] Voltage-Triggered ESD Power Clamps	p. 318
8.5.4 Mixed Voltage Interface Forward-Bias Voltage and BV[subscript CEO] Breakdown Synthesized Bipolar ESD Power Clamps	p. 323
8.5.5 Ultra-Low Voltage Forward-Biased Voltage-Trigger BiCMOS ESD Power Clamps	p. 328
8.5.6 Capacitively Triggered BiCMOS ESD Power Clamps	p. 332
8.6 Bipolar ESD Diode String and Triple-Well Power Clamps	p. 334
8.7 Summary and Closing Comments	p. 335
Problems	p. 335
References	p. 337
Chapter 9 RF and ESD Computer-Aided Design (CAD)	p. 339
9.1 RF ESD Design Environment	p. 339
9.1.1 Electrostatic Discharge and Radio Frequency (RF) Cosynthesis Design Methods	p. 339
9.1.2 ESD Hierarchical Pcell Physical Layout Generation	p. 340
9.1.3 ESD Hierarchical Pcell Schematic Generation	p. 341
9.2 ESD Design with Hierarchical Parameterized Cells	p. 341
9.2.1 Hierarchical Pcell Graphical Method	p. 342
9.2.2 Hierarchical Pcell Schematic Method	p. 344
9.3 ESD Design of RF CMOS-Based Hierarchical Parameterized Cells	p. 347
9.4 RF BiCMOS ESD Hierarchical Parameterized Cell	p. 349
9.4.1 BiCMOS ESD Input Networks	p. 350
9.4.2 BiCMOS ESD Rail-to-Rail	p. 353
9.4.3 BiCMOS ESD Power Clamps	p. 354
9.5 Advantages and Limitations of the RF ESD Design System	p. 359
9.6 Guard Ring P-Cell Methodology	p. 362
9.6.1 Guard Rings for Internal and External Latchup Phenomena	p. 362
9.6.2 Guard Ring Theory	p. 363
9.6.3 Guard Ring Design	p. 365
9.6.4 Guard Ring Characterization	p. 367
9.7 Summary and Closing Comments	p. 370
Problems	p. 370
References	p. 371
Chapter 10 Alternative ESD Concepts: On-Chip and Off-Chip ESD Protection Solutions	p. 375
10.1 Spark Gaps	p. 375
10.2 Field Emission Devices	p. 378
10.2.1 Field Emission Device (FED) as ESD Protection	p. 378
10.2.2 Field Emission Device in Gallium Arsenide Technology	p. 379
10.2.3 Field Emission Device Electronic Blunting Effect	p. 380
10.2.4 Field Emission Device Multiemitter ESD Design	p. 380
10.2.5 Field Emission Device (FED) ESD Design Practices	p. 382
10.3 Off-Chip Protection and Off-Chip Transient Suppression Devices	p. 382
10.3.1 Off-Chip Transient Voltage Suppression (TVS) Devices	p. 383
10.3.2 Off-Chip Polymer Voltage Suppression (PVS) Devices	p. 384
10.4 Package-Level Mechanical ESD Solutions	p. 386
10.5 RE Proximity Communications Chip-to-Chip ESD Design Practices	p. 387
10.6 Summary and Closing Comments	p. 388
Problems	p. 389
References	p. 389
Index	p. 391

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