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Summary
Summary
From the explosion of interest, research, and applications of evolutionary computation a new field emerges-evolutionary electronics. Focused on applying evolutionary computation concepts and techniques to the domain of electronics, many researchers now see it as holding the greatest potential for overcoming the drawbacks of conventional design techniques.
Evolutionary Electronics: Automatic Design of Electronic Circuits and Systems by Genetic Algorithms formally introduces and defines this area of research, presents its main challenges in electronic design, and explores emerging technologies. It describes the evolutionary computation paradigm and its primary algorithms, and explores topics of current interest, such as multi-objective optimization. The authors examine numerous evolutionary electronics applications, draw conclusions about those applications, and sketch the future of evolutionary computation and its applications in electronics.
In coming years, the appearance of more and more advanced technologies will increase the complexity of optimization and synthesis problems, and evolutionary electronics will almost certainly become a key to solving those problems. Evolutionary Electronics is your key to discovering and unlocking the potential of this promising new field.
Table of Contents
Unit I Introduction | |
Chapter 1 Introduction to Evolutionary Electronics | p. 1 |
1.1 Evolutionary Design of Electronic Circuits: A Prospect of the Area | p. 1 |
1.2 Electronic Circuit Design: A Search Task | p. 6 |
1.3 A Brief Survey of Evolutionary Electronics | p. 9 |
Unit II Evolutionary Computation | |
Chapter 2 Introduction to Evolutionary Computation | p. 15 |
2.1 Basic Concepts of Natural Evolution | p. 15 |
2.1.1 The Evolutionary Hypothesis | p. 15 |
2.1.2 Molecular Genetics | p. 17 |
2.1.3 Recombination and Mutation | p. 20 |
2.1.4 Mendelian Ratios | p. 21 |
2.1.5 The Evidences of Evolution | p. 23 |
2.2 Putting the Ideas to Work: Evolutionary Computation | p. 25 |
2.2.1 Representation | p. 27 |
2.2.2 Evaluation | p. 32 |
2.2.3 Main Operators | p. 32 |
2.2.3.1 Selection | p. 32 |
2.2.3.2 Crossover | p. 34 |
2.2.3.3 Mutation | p. 36 |
2.3 The Main Evolutionary Algorithms | p. 37 |
2.3.1 Evolutionary Programming (EP) | p. 37 |
2.3.2 Evolutionary Strategies (ES) | p. 38 |
2.3.3 Genetic Algorithms (GAs) | p. 39 |
2.3.4 Genetic Programming (GP) | p. 44 |
Chapter 3 Advanced Topics in Evolutionary Computation | p. 53 |
3.1 Variable Length Representation Systems | p. 53 |
3.1.1 Representation in Natural Systems | p. 54 |
3.1.2 Representation in Artificial Systems | p. 55 |
3.1.3 Genetic Algorithms with Variable Length Representation | p. 56 |
3.2 Evolutionary Algorithms Using the Memory Paradigm | p. 64 |
3.3 Multiple-Objective Optimization | p. 65 |
3.3.1 Evolutionary Computation Applied to Multi-Objective Optimization | p. 66 |
3.3.1.1 Plain Aggregating Approaches | p. 67 |
3.3.1.2 Population-Based Non-Pareto Approaches | p. 67 |
3.3.1.3 Pareto-Based Approaches | p. 68 |
3.3.2 A New Approach for Multi-Objective Optimization: Energy Minimi zation Strategy | p. 69 |
3.4 Speciation in Evolutionary Algorithms | p. 73 |
3.5 Deception and Epistasy | p. 76 |
3.5.1 Epistasy | p. 79 |
Unit III Evolutionary Electronics | |
Chapter 4 Evolutionary Computation: A Tool for Computed-Aided Design of electronic Ciruits | p. 91 |
4.1 Optimization of Analog Vlsi Chips | p. 91 |
4.1.1 OpAmp Design Optimization | p. 92 |
4.1.2 Problem Representation | p. 93 |
4.1.3 Genetic Operators | p. 94 |
4.1.4 Fitness Evaluation Function | p. 94 |
4.1.5 Case Studies | p. 95 |
4.1.5.1 Miller CMOS OTA: GAs Rediscovering Human Design | p. 95 |
4.1.5.2 Low Power Operational Amplifiers: New Design Strategies | p. 98 |
4.1.5.3 Synthesis of BiCMOS Amplifiers | p. 104 |
4.2 Digital Vlsi Design and Layout Optimization | p. 106 |
4.2.1 Logic Synthesis | p. 107 |
4.2.2 Technology Mapping and Physical Design | p. 109 |
4.2.3 Testing | p. 113 |
4.3 Summary | p. 116 |
Chapter 5 Evolutionary Computation: A Tool for Analog Electronic Circuit Synthesis | p. 119 |
5.1 Analog Circuits Evolution | p. 119 |
5.1.1 Synthesis of Passive Filters | p. 120 |
5.1.1.1 Passive Filters: Basic Concepts | p. 120 |
5.1.1.2 Representation | p. 122 |
5.1.1.3 Fitness Evaluation | p. 124 |
5.1.1.4 Case Study: Low Pass Brick-Wall Filter | p. 125 |
5.1.1.5 Other Evolutionary Approaches | p. 128 |
5.1.1.5.1 Genetic Programming | p. 129 |
5.1.1.5.2 Genetic Algorithm with Developmental Representation | p. 136 |
5.1.2 Synthesis of Active Filters | p. 140 |
5.1.2.1 Problem Description | p. 141 |
5.1.2.2 Representation | p. 142 |
5.1.2.3 Evaluation | p. 142 |
5.1.2.4 Case Studies | p. 143 |
5.1.2.4.1 Single Objective Experiments | p. 143 |
5.1.2.4.2 Multi-Objective Experiments: First Case | p. 146 |
5.1.2.4.3 Multi-Objective Experiments: Second Case | p. 149 |
5.1.3 Synthesis of Operational Amplifiers Based on Bipolar Technology | p. 152 |
5.1.3.1 Problem Description | p. 152 |
5.1.3.2 Representation | p. 153 |
5.1.3.3 Evaluation | p. 153 |
5.1.3.4 Case Studies | p. 154 |
5.1.4 Synthesis of a Digital to Analog Converter (DAC) | p. 159 |
Chapter 6 Evolutionary Computation: A Tool for Digital Circuit Synthesis | p. 165 |
6.1 Representation | p. 166 |
6.1.1 Functional Level Representation | p. 166 |
6.1.2 Gate Level Representation | p. 171 |
6.1.3 Transistor Level Representation | p. 173 |
6.2 Fitness Evaluation Function | p. 174 |
6.3 Case Studies | p. 177 |
6.3.1 Combinational Circuits | p. 177 |
6.3.1.1 Multiplexers and Parity Circuits | p. 177 |
6.3.1.2 Arithmetic Circuits | p. 180 |
6.3.1.2.1 Sum of Products Representation | p. 181 |
6.3.1.2.2 Use of Reverse Logic and Incremental Evolution | p. 182 |
6.3.1.2.3 Adders and Multipliers | p. 185 |
6.3.2 Synthesis of Sequential Circuits | p. 188 |
6.3.3 Transistor Logic | p. 190 |
6.3.4 Digital Filters | p. 194 |
6.3.4.1 Basic Concepts | p. 195 |
6.3.4.2 Functional and Gate Level Representation | p. 195 |
6.3.4.3 Functional Level Representation in The Synthesis of Multiplier-Less Filters | p. 196 |
6.3.4.3.1 Gate Level Representation | p. 199 |
Chapter 7 Evolution of Circuits on Reconfigurable Chips | p. 205 |
7.1 Programmable Logic Devices | p. 206 |
7.1.1 Prom | p. 207 |
7.1.2 Programmable Logic Array (PLA) | p. 208 |
7.1.3 Programmable Array Logic | p. 210 |
7.1.4 Field Programmable Digital Arrays (FPGAs) | p. 211 |
7.2 Field Programmable Analog Arrays (FPAAs) | p. 214 |
7.2.1 Totally Reconfigurable Analog Hardware | p. 215 |
7.2.2 Motorola | p. 215 |
7.2.3 Palmo (University of Edinburgh) | p. 217 |
7.2.4 Evolvable Motherboard (University of Sussex) | p. 219 |
7.2.5 Programmable Transistor Array (PTA) (Jet Propulsion Lab) | p. 220 |
7.2.6 Programmable Analog Multiplexer Array (PAMA) (Catholic University of Rio de Janeiro) | p. 222 |
7.2.7 Lattice PAC | p. 224 |
7.2.8 Comparative Table | p. 224 |
7.3 Evolvable Hardware | p. 225 |
7.3.1 Thompson | p. 225 |
7.3.1.1 Experimental Setup | p. 226 |
7.3.1.2 Results | p. 227 |
7.3.1.3 Analysis | p. 230 |
7.3.2 Stoica et al. | p. 232 |
7.3.3 Zebulum et al. (2000) | p. 234 |
7.3.4 Zebulum et al. (1999) | p. 238 |
7.4 Virtual Computing | p. 241 |
Chapter 8 Advanced Topics of Evolutionary Electronics: Filtering, Control, Antennas, and Fault Tolerance | p. 245 |
8.1 Active Filters | p. 245 |
8.2 Control Applications | p. 247 |
8.2.1 Evolution of Control Circuits Using Genetic Algorithms | p. 247 |
8.2.1.1 Representation | p. 247 |
8.2.1.2 Evaluation | p. 247 |
8.2.1.3 First Experiment | p. 249 |
8.2.1.4 Lessons Learned | p. 256 |
8.2.2 Evolution of PID controllers by Means of Genetic Programming | p. 257 |
8.2.2.1 Representation | p. 257 |
8.2.2.2 Fitness Evaluation Function | p. 259 |
8.2.2.3 Results | p. 260 |
8.2.3 Comparison | p. 260 |
8.3 Evolution of Antennas | p. 261 |
8.3.1 Overview of Antennas | p. 261 |
8.3.2 Evolution of Antennas Through GAs | p. 263 |
8.3.2.1 Problem Specification | p. 263 |
8.3.2.2 Representation | p. 263 |
8.3.2.3 Fitness Evaluation Function | p. 263 |
8.3.3 Evolution of Antennas Through GP | p. 264 |
8.3.3.1 Problem Specification | p. 264 |
8.3.3.2 Representation | p. 264 |
8.3.3.3 Fitness Evaluation Function | p. 265 |
8.3.3.4 Results | p. 265 |
8.4 Fault Tolerance and Evolutionary Electronics | p. 265 |
8.4.1 Implicit Fault Tolerance | p. 266 |
8.4.2 Explicit Fault Tolerance | p. 268 |
8.4.3 A Comparison between Implicit and Explicit Fault Tolerance Tech niques | p. 270 |
8.5 Summary | p. 272 |
Unit IV Conclusions | |
Chapter 9 Conclusions | p. 275 |
9.1 Evolutionary and Conventional Design | p. 275 |
9.2 Programmable Circuits | p. 275 |
9.3 Consequences on Analog and Digital Electronics | p. 277 |
9.4 Fault Tolerant Systems | p. 278 |
Appendix A Mos Transistors | p. 281 |
Appendix B Switched Capacitor (SC) Circuits | p. 285 |
Appendix C Gm-C Filters | p. 287 |
Appendix D An Introduction to Nano Electronics | p. 289 |
Index | p. 295 |