Autonomic networking-on-chip : bio-inspired specification, development, and verification

Title:

Series:

Embedded multi-core systems

Publication Information:

Boca Raton, Fla. : CRC Press, c2012

Physical Description:

xxvi, 261 p. : ill. ; 24 cm.

ISBN:

9781439829110

Subject Term:

Networks on a chip

Autonomic computing

Added Author:

Cong-Vinh, Phan

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010332670	TK5105.546 A86 2012	Open Access Book	Book	Searching... Unknown

Despite the growing mainstream importance and unique advantages of autonomic networking-on-chip (ANoC) technology, Autonomic Networking-On-Chip: Bio-Inspired Specification, Development, and Verification is among the first books to evaluate research results on formalizing this emerging NoC paradigm, which was inspired by the human nervous system.

The FIRST Book to Assess Research Results, Opportunities, & Trends in "BioChipNets"

The third book in the Embedded Multi-Core Systems series from CRC Press, this is an advanced technical guide and reference composed of contributions from prominent researchers in industry and academia around the world. A response to the critical need for a global information exchange and dialogue, it is written for engineers, scientists, practitioners, and other researchers who have a basic understanding of NoC and are now ready to learn how to specify, develop, and verify ANoC using rigorous approaches.

Offers Expert Insights Into Technical Topics Including:

Bio-inspired NoC How to map applications onto ANoC ANoC for FPGAs and structured ASICs Methods to apply formal methods in ANoC development Ways to formalize languages that enable ANoC Methods to validate and verify techniques for ANoC Use of "self-" processes in ANoC (self-organization, configuration, healing, optimization, protection, etc.) Use of calculi for reasoning about context awareness and programming models in ANoC

With illustrative figures to simplify contents and enhance understanding, this resource contains original, peer-reviewed chapters reporting on new developments and opportunities, emerging trends, and open research problems of interest to both the autonomic computing and network-on-chip communities. Coverage includes state-of-the-art ANoC architectures, protocols, technologies, and applications. This volume thoroughly explores the theory behind ANoC to illustrate strategies that enable readers to use formal ANoC methods yet still make sound judgments and allow for reasonable justifications in practice.

Author Notes

Phan Cong-Vinh received a Ph.D in computer science from London South Bank University (LSBU) in the United Kingdom, a BS in mathematics and an MS in computer science from Vietnam National University (VNU) in Ho Chi Minh City, and a BA in English from Hanoi University of Foreign Languages Studies in Vietnam. He finished his PhD dissertation with the title Formal Aspects of Dynamic Reconfigurability in Reconfigurable Computing Systems supervised by Prof. Jonathan P. Bowen at LSBU where he was affiliated with the Centre for Applied Formal Methods (CAFM) at the Institute for Computing Research (ICR). From 1983 to 2000, he was a lecturer in mathematics and computer science at VNU, Posts and Telecommunications Institute of Technology (PTIT) and several other universities in Vietnam before he joined research with Dr. Tomasz Janowski at the International Institute for Software Technology (IIST) in Macao SAR, China, as a fellow in 2000. His research interests center on all aspects of formal methods, autonomic computing and networking, reconfigurable computing, ubiquitous computing, and applied categorical structures in computer science.

M. BakhouyaA. A. Morgan and H. Elmiligi and M. W. El-Kliarashi and F. GebaliK. Latif and A. M. Rahmani and T. Seceleanu and H. TenhanenJ. Jams and V. DvorakP. C. VinhL. Guang and J. Plosila and J. Isoaho and H. TenhunenL. Petre and K. Sere and L. Tsiopoulos and P. Liljeberg and J. PlosilaH. Zakaria and E. Yahya and L. Fesquet

List of Figures	p. xi
List of Tables	p. xv
Foreword	p. xvii
Preface	p. xix
About the Editor	p. xxiii
List of Contributors	p. xxv
1 A Bio-Inspired Architecture for Autonomic Network-on-Chip	p. 1
1.1 Introduction	p. 2
1.2 Infrastructure level	p. 3
1.2.1 Topology customization	p. 4
1.2.2 Bandwidth allocation	p. 5
1.2.3 Buffer allocation	p. 6
1.3 Communication level	p. 7
1.3.1 Switching modes	p. 7
1.3.2 Routing schemes	p. 8
1.3.3 Flow control schemes	p. 9
1.4 Application level	p. 11
1.5 BNoC Architecture	p. 12
1.5.1 Immune system principles	p. 13
1.5.2 BNoC principles	p. 14
1.5.3 Simulation results	p. 16
1.6 Conclusions	p. 19
2 Bio-Inspired NoC Architecture Optimization	p. 21
2.1 Introduction	p. 22
2.2 Related work	p. 23
2.2.1 Employment of known standard architectures	p. 24
2.2.2 Generation of semi-custom architectures	p. 24
2.2.3 Generation of fully-custom architectures	p. 25
2.3 Bio-inspired optimization techniques	p. 25
2.4 Graph theory representation of NoC applications	p. 26
2.5 Problem formulation	p. 26
2.5.1 Power model	p. 28
2.5.2 Area model	p. 30
2.5.3 Delay model	p. 31
2.5.4 Reliability model	p. 32
2.5.5 Optimization objective function formulation	p. 32
2.6 Custom architecture generation using GA	p. 33
2.6.1 Legality criteria for generated architectures	p. 34
2.6.2 Methodology for custom architecture generation	p. 36
2.7 Experimental results	p. 38
2.8 Conclusions	p. 45
3 An Autonomic NoC Architecture Using Heuristic Technique for Virtual-Channel Sharing	p. 47
3.1 Introduction	p. 48
3.2 Background	p. 51
3.3 Resource utilization analysis	p. 52
3.3.1 Link load analysis	p. 52
3.3.2 Real application-based analysis	p. 53
3.4 The proposed router architecture: PVS-NoC	p. 54
3.4.1 Packet format	p. 56
3.4.2 The input controller and buffer allocation	p. 58
3.4.3 The output controller and routing algorithm	p. 60
3.4.4 Comparison with existing architectures	p. 61
3.4.5 Virtual-channel sharing under faults	p. 63
3.5 Experimental results	p. 64
3.5.1 Synthetic traffic	p. 65
3.5.2 Real application traffic	p. 65
3.6 Conclusions	p. 66
3.7 Glossary	p. 68
4 Evolutionary Design of Collective Communications on Wormhole NoCs	p. 69
4.1 Introduction	p. 70
4.2 Collective communications	p. 71
4.2.1 A model of communication	p. 72
4.2.2 Classification of collective communications	p. 74
4.2.3 The lower bounds on time complexity	p. 75
4.3 State-of-the-art	p. 77
4.4 Evolutionary design of collective communications	p. 78
4.4.1 Input data structure and preprocessing	p. 80
4.4.2 Scatter encoding	p. 80
4.4.3 Broadcast encoding	p. 81
4.4.4 Fitness function definition	p. 83
4.4.5 Acceleration and restoration heuristics	p. 84
4.4.6 The mutation operator	p. 84
4.5 Optimization tools and parameters adjustments	p. 85
4.5.1 Experimental comparison of optimization quality	p. 86
4.5.2 Experimental comparison of optimization speed	p. 86
4.5.3 Experimental comparison of optimization scalability ....	p. 87
4.5.4 Tools assessment	p. 89
4.6 Experimental results of the quest for high-quality schedules ....	p. 89
4.6.1 Experimental results on common topologies	p. 89
4.6.1 Experimental results on novel and fat nodes topologies	p. 91
4.6.1 Experimental results on fault-tolerant topologies and many-to-many patterns	p. 94
4.7 Conclusions	p. 98
4.7.1 Contributions of the proposed technique	p. 101
4.7.2 Future work	p. 102
5 Formal Aspects of Parallel Processing on Bio-Inspired on-Chip Networks	p. 105
5.1 Introduction	p. 106
5.2 Outline	p. 108
5.3 Related work	p. 108
5.4 Basic concepts	p. 109
5.4.1 Category definition	p. 109
5.4.1.1 Category as a graph	p. 109
5.4.1.2 Identity morphism and composition of morphisms	p. 110
5.4.1.3 Identity and associativity for composition of morphisms	p. 112
5.4.2 Functor	p. 112
5.4.3 Isomorphism	p. 112
5.4.4 Natural isomorphism	p. 113
5.4.5 Element of a set	p. 113
5.5 Processing BioChipNet tasks	p. 114
5.5.1 Parallel composition of BioChipNet tasks	p. 114
5.5.2 BioChipNet Tasks	p. 115
5.5.3 Categorical characteristics of BioChipNet tasks	p. 116
5.5.4 Core-to-core networks	p. 118
5.5.4.1 Self-configuration of core-to-core networks	p. 118
5.5.4.2 Category of core-to-core networks	p. 120
5.5.4.3 Extensional monoidal category of core-to-core networks	p. 121
5.5.4.4 Pushout of self-configuring core-to-core networks	p. 122
5.6 Processing BioChipNet data .	p. 124
5.6.1 BioChipNet agents	p. 124
5.6.2 Category of BioChipNet data types	p. 126
5.6.3 Extensional monoidal category of BioChipNet data types	p. 127
5.6.4 Parallel composition of BioChipNet agents	p. 129
5.7 Notes and remarks	p. 132
5.8 Conclusions	p. 134
6 HAMSoC: A Monitoring-Centric Design Approach for Adaptive Parallel Computing	p. 135
6.1 Introduction	p. 136
6.2 Hierarchical agent monitoring design approach	p. 137
6.2.1 Monitoring-centric design methodology	p. 137
6.2.2 Hierarchical agent monitoring	p. 139
6.2.3 Hierarchical agent monitored system-on-chip	p. 141
6.3 Formal specification of HAMSoC	p. 144
6.3.1 Specification framework of HAMSoC	p. 144
6.3.2 Specification of agents and resources	p. 147
6.3.2.1 Formal specification of resources	p. 147
6.3.2.2 Formal specification of agents	p. 149
6.3.3 Specification of monitoring operations	p. 150
6.3.3.1 Specification format	p. 150
6.3.3.2 Types of monitoring operation	p. 151
6.3.4 State transition of agents and resources	p. 152
6.3.4.1 State transition of resources	p. 153
6.3.4.2 State transition of agents	p. 155
6.4 Design example: hierarchical power monitoring in HAMNoC	p. 156
6.4.1 System description	p. 157
6.4.2 Specification of resources	p. 159
6.4.3 Specification of agents and monitoring operations	p. 159
6.4.4 Formal modeling of state transitions	p. 161
6.5 Conclusions	p. 163
6.6 Glossary	p. 164
7 Toward Self-Placing Applications on 2D and 3D NoCs	p. 165
7.1 Introduction	p. 165
7.2 Related work	p. 168
7.3 NoC-oriented MTDAS	p. 172
7.3.1 Conservative extension	p. 174
7.3.2 Enabledness	p. 176
7.3.3 Location-updating code	p. 178
7.3.4 Updating replicated memory units	p. 179
7.4 Placing and replacing resources	p. 179
7.4.1 The placing algorithm	p. 179
7.4.2 Replacing	p. 183
7.5 Conclusions	p. 187
8 Self-Adaption in SoCs	p. 189
8.1 Introduction	p. 190
8.1.1 Power consumption	p. 190
8.1.2 Process variability	p. 191
8.1.3 Yield	p. 192
8.2 Power management techniques	p. 193
8.2.1 Leakage power management	p. 194
8.2.2 Dynamic power management	p. 194
8.2.2.1 DVFS architecture overview	p. 197
8.2.2.2 DC/DC converter	p. 200
8.2.2.3 Clock generator	p. 201
8.2.2.4 Sensing the computational activity	p. 202
8.3 Controlling uncertainty and handling process variability	p. 203
8.4 Data synchronization in GALS system	p. 207
8.4.1 GALS wrapper with pausible clocking	p. 208
8.4.2 FIFO solutions	p. 209
8.4.3 Boundary synchronization	p. 210
8.5 Conclusions	p. 212
8.6 Glossary	p. 213
Bibliography	p. 215
Index	p. 243

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