VHDL-2008 : just the new stuff

VHDL-2008: Just the New Stuff, as its title says, introduces the new features added to the latest revision of the IEEE standard for the VHDL hardware description language. Written by the Chair and Technical Editor of the IEEE working group, the book is an authoritative guide to how the new features work and how to use them to improve design productivity. It will be invaluable for early adopters of the new language version, for tool implementers, and for those just curious about where VHDL is headed.

Author Notes

Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.

Preface	p. ix
1 Enhanced Generics	p. 1
1.1 Generic Types	p. 1
1.2 Generic Lists in Packages	p. 6
1.3 Local Packages	p. 11
1.4 Generic Lists in Subprograms	p. 15
1.5 Generic Subprograms	p. 21
1.5.1 Uninstantiated Methods in Protected Types	p. 32
1.6 Generic Packages	p. 36
1.7 Use Case: Generic Memories	p. 43
2 Other Major Features	p. 53
2.1 External Names	p. 53
2.2 Force and Release	p. 63
2.3 Context Declarations	p. 67
2.4 Integrated PSL	p. 70
2.5 IP Encryption	p. 77
2.5.1 Key Exchange	p. 96
2.6 VHDL Procedural Interface (VHPI)	p. 97
2.6.1 Direct Binding	p. 97
2.6.2 Tabular Registration and Indirect Binding	p. 99
2.6.3 Registration of Applications and Libraries	p. 101
3 Type System Changes	p. 103
3.1 Unconstrained Element Types	p. 103
3.1.1 Composite Types	p. 103
3.1.2 Subtype Indications and Constraints	p. 107
3.1.3 Use of Composite Subtypes	p. 109
Variable and Signal Declarations	p. 110
Constant Declarations	p. 110
Attribute Specifications	p. 111
Allocated Objects	p. 111
Interface Objects	p. 112
Summary: Determining Array Index Ranges	p. 117
Type Conversions	p. 118
Alias Declarations and Subtype Attributes	p. 119
Resolved Composite Subtypes	p. 122
3.2 Resolved Elements	p. 123
4 New and Changed Operations	p. 127
4.1 Array/Scalar Logical Operations	p. 127
4.2 Array/Scalar Addition Operators	p. 129
4.3 Logical Reduction Operators	p. 130
4.4 Condition Operator	p. 132
4.5 Matching Relational Operators	p. 133
4.6 Maximum and Minimum	p. 138
4.7 Mod and Rem for Physical Types	p. 140
4.8 Shift Operations	p. 141
4.9 Strength Reduction and 'X' Detection	p. 142
5 New and Changed Statements	p. 143
5.1 Conditional and Selected Assignments	p. 143
5.1.1 Sequential Signal Assignments	p. 143
5.1.2 Forcing Assignments	p. 146
5.1.3 Variable Assignments	p. 147
5.2 Matching Case Statements	p. 149
5.2.1 Matching Selected Assignments	p. 150
5.3 If and Case Generate	p. 151
5.3.1 Configuration of If and Case Generate	p. 155
6 Modeling Enhancements	p. 159
6.1 Signal Expressions in Port Maps	p. 159
6.2 All Signals in Sensitivity List	p. 161
6.3 Reading Out-Mode Ports and Parameters	p. 162
6.4 Slices in Aggregates	p. 166
6.5 Bit-String Literals	p. 167
7 Improved I/O	p. 169
7.1 The To_String Functions	p. 169
7.1.1 Predefined To_string Functions	p. 170
7.1.2 Overloaded To_string Functions	p. 171
7.1.3 The To_ostring and To_hstring Functions	p. 172
7.2 The Justify Function	p. 173
7.3 Newline Formatting	p. 173
7.4 Read and Write Operations	p. 174
7.5 The Tee Procedure	p. 177
7.6 The Flush Procedure	p. 178
8 Standard Packages	p. 179
8.1 The Std_logic_1 164 Package	p. 179
8.2 The Numeric_bit and Numeric_std Packages	p. 180
8.3 The Numeric Unsigned Packages	p. 182
8.4 The Fixed-Point Math Packages	p. 182
8.5 The Floating-Point Math Packages	p. 186
8.6 The Standard Package	p. 191
8.7 The Env Package	p. 192
8.8 Operator Overloading Summary	p. 193
8.9 Conversion Function Summary	p. 196
8.10 Strength Reduction Function Summary	p. 204
9 Miscellaneous Changes	p. 207
9.1 Referencing Generics in Generic Lists	p. 207
9.2 Function Return Subtype	p. 208
9.3 Qualified Expression Subtype	p. 209
9.4 Type Conversions	p. 209
9.5 Case Expression Subtype	p. 211
9.6 Subtypes for Port and Parameter Actuals	p. 212
9.7 Static Composite Expressions	p. 213
9.8 Static Ranges	p. 214
9.9 Use Clauses, Types, and Operations	p. 215
9.10 Hiding of Implicit Operations	p. 216
9.11 Multidimensional Array Alias	p. 217
9.12 Others in Aggregates	p. 217
9.13 Attribute Specifications in Package Bodies	p. 219
9.14 Attribute Specification for Overloaded Subprograms	p. 219
9.15 Integer Expressions in Range Bounds	p. 220
9.16 Action on Assertion Violations	p. 221
9.17 'Path_Name and 'Instance_Name	p. 221
9.18 Non-Nesting of Architecture Region	p. 223
9.19 Purity of Now	p. 223
9.20 Delimited Comments	p. 224
9.21 Tool Directives	p. 225
9.22 New Reserved Words	p. 225
9.23 Replacement Characters	p. 226
10 What's Next	p. 229
10.1 Object-Oriented Class Types	p. 229
10.1.1 Standard Components Library	p. 232
10.2 Randomization	p. 232
10.3 Functional Coverage	p. 235
10.4 Alternatives	p. 235
10.5 Getting Involved	p. 235
Index	p. 237

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Author Notes

Table of Contents