Cover image for Ladder logic processor for programmable logic controllers (PLC) on fileld programmable gated array (FPGA)
Title:
Ladder logic processor for programmable logic controllers (PLC) on fileld programmable gated array (FPGA)
Personal Author:
Publication Information:
2007
Physical Description:
xiv, 58p. : ill. ; 30 cm. + 1 CD-ROM
General Note:
Supervisor : Zulfakar Aspar

Also available in CD-ROM : CP 019333 ra
Added Author:
Added Corporate Author:
DSP_DISSERTATION:
Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2007

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FKE30000003171 TK7868.D5 C485 2007 raf Closed Access Thesis UTM Project Paper (Closed Access)
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30000010154018 TK7868.D5 C485 2007 raf Closed Access Thesis UTM Project Paper (Closed Access)
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