VLSI design of 8X8 BIT unsigned parallel multiplier using L. Dadda reduction tree method

Select an Action

Place Hold(s)
Add to My Lists
Email
Print

Cover image for VLSI design of 8X8 BIT unsigned parallel multiplier using L. Dadda reduction tree method

Title:

VLSI design of 8X8 BIT unsigned parallel multiplier using L. Dadda reduction tree method

Personal Author:

Fadzlan Mohamad

Publication Information:

2004

Physical Description:

xv, 120 p. : ill. ; 30 cm.

General Note:

Also available in CD-ROM : CP 018534 ra

Subject Term:

Integrated circuits -- Very large scale integration

Parallel processing (Electronic computers)

Added Corporate Author:

Fakulti Kejuruteraan Elektrik

DSP_DISSERTATION:

Project Paper (Sarjana Muda Kejuruteraan (Elektrik - Elektronik)) - Universiti Teknologi Malaysia, 2004

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... FKE Library	FKE30000001452	QA76.58 F32 2004	Closed Access Thesis	UTM Project Paper (Closed Access)	Searching... Unknown
Searching... Perpustakaan Raja Zarith Sofiah	30000010033913	QA76.58 F32 2004 raf	Closed Access Thesis	UTM Project Paper (Closed Access)	Searching... Unknown

On Order