FSM-based digital design using Verilog HDL

As digital circuit elements decrease in physical size, resulting in increasingly complex systems, a basic logic model that can be used in the control and design of a range of semiconductor devices is vital. Finite State Machines (FSM) have numerous advantages; they can be applied to many areas (including motor control, and signal and serial data identification to name a few) and they use less logic than their alternatives, leading to the development of faster digital hardware systems.

This clear and logical book presents a range of novel techniques for the rapid and reliable design of digital systems using FSMs, detailing exactly how and where they can be implemented. With a practical approach, it covers synchronous and asynchronous FSMs in the design of both simple and complex systems, and Petri-Net design techniques for sequential/parallel control systems. Chapters on Hardware Description Language cover the widely-used and powerful Verilog HDL in sufficient detail to facilitate the description and verification of FSMs, and FSM based systems, at both the gate and behavioural levels.

Throughout, the text incorporates many real-world examples that demonstrate designs such as data acquisition, a memory tester, and passive serial data monitoring and detection, among others. A useful accompanying CD offers working Verilog software tools for the capture and simulation of design solutions.

With a linear programmed learning format, this book works as a concise guide for the practising digital designer. This book will also be of importance to senior students and postgraduates of electronic engineering, who require design skills for the embedded systems market.

Author Notes

Peter D. Minns, Northumbria University, School of Computing, Engineering, and Information Sciences, Newcastle Upon Tyne
Dr Peter Minns has been at Northumbria University since 1984, now holding the position of Senior Lecturer in the School of Computing, Engineering and Information Sciences. He teaches courses on electrical circuit theory, electronics, programming and embedded system design to both undergraduates and post graduates, and is also involved in teaching company schemes in industry. Previous to this, he has worked for many years as a practising engineer specializing in both the telecommunications and embedded microprocessor fields. His current research interest is in the development of finite state machines (FSMs).

Ian David Elliott, Northumbria University, School of Computing, Engineering, and Information Sciences, Newcastle Upon Tyne
Ian Elliott has been a lecturer in further and higher education for over 20 years, currently holding the position of Senior Lecturer in the School of Computing, Engineering and Information Sciences, at Northumbria University. He has taught a wide range of subjects in the field of electronics, as well as working as a consultant in industry, carrying out research into integrated circuit testing. He now specializes in hardware description languages, specifically Verilog-HDL and Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). He was one of the first academics to introduce the topic of hardware description languages into the curriculum.

Preface	p. xi
Acknowledgements	p. xv
1 Introduction to Finite-State Machines and State Diagrams for the Design of Electronic Circuits and Systems	p. 1
1.1 Introduction	p. 1
1.2 Learning Material	p. 2
1.3 Summary	p. 21
2 Using State Diagrams to Control External Hardware Subsystems	p. 23
2.1 Introduction	p. 23
2.2 Learning Material	p. 23
2.3 Summary	p. 38
3 Synthesizing Hardware from a State Diagram	p. 39
3.1 Introduction to Finite-State Machine Synthesis	p. 39
3.2 Learning Material	p. 40
3.3 Summary	p. 66
4 Synchronous Finite-State Machine Designs	p. 67
4.1 Traditional State Diagram Synthesis Method	p. 67
4.2 Dealing with Unused States	p. 69
4.3 Development of a High/Low Alarm Indicator System	p. 71
4.3.1 Testing the Finite-State Machine using a Test-Bench Module	p. 75
4.4 Simple Waveform Generator	p. 76
4.4.1 Sampling Frequency and Samples per Waveform	p. 78
4.5 The Dice Game	p. 79
4.5.1 Development of the Equations for the Dice Game	p. 81
4.6 Binary Data Serial Transmitter	p. 83
4.6.1 The RE Counter Block in the Shift Register of Figure 4.15	p. 87
4.7 Development of a Serial Asynchronous Receiver	p. 88
4.7.1 Finite-State Machine Equations	p. 91
4.8 Adding Parity Detection to the Serial Receiver System	p. 92
4.8.1 To Incorporate the Parity	p. 92
4.8.2 D-Type Equations for Figure 4.26	p. 94
4.9 An Asynchronous Serial Transmitter System	p. 95
4.9.1 Equations for the Asynchronous Serial Transmitter	p. 98
4.10 Clocked Watchdog Timer	p. 100
4.10.1 D Flip-Flop Equations	p. 102
4.10.2 Output Equation	p. 102
4.11 Summary	p. 103
5 The One Hot Technique in Finite-State Machine Design	p. 105
5.1 The One Hot Technique	p. 105
5.2 A Data Acquisition System	p. 110
5.3 A Shared Memory System	p. 114
5.4 Fast Waveform Synthesizer	p. 116
5.4.1 Specification	p. 117
5.4.2 A Possible Solution	p. 118
5.4.3 Equations for the d Inputs to D Flip-Flops	p. 119
5.4.4 Output Equations	p. 120
5.5 Controlling the Finite-State Machine from a Microprocessor/Microcontroller	p. 120
5.6 A Memory-Chip Tester	p. 123
5.7 Comparing One Hot with the more Conventional Design Method of Chapter 4	p. 126
5.8 A Dynamic Memory Access Controller	p. 127
5.8.1 Flip-Flop Equations	p. 131
5.8.2 Output Equations	p. 131
5.9 How to Control the Dynamic Memory Access from a Microprocessor	p. 132
5.10 Detecting Sequential Binary Sequences using a Finite-State Machine	p. 134
5.11 Summary	p. 143
6 Introduction to Verilog HDL	p. 145
6.1 A Brief Background to Hardware Description Languages	p. 145
6.2 Hardware Modelling with Verilog HDL: the Module	p. 147
6.3 Modules within Modules: Creating Hierarchy	p. 152
6.4 Verilog HDL Simulation: a Complete Example	p. 155
References	p. 162
7 Elements of Verilog HDL	p. 163
7.1 Built-In Primitives and Types	p. 163
7.1.1 Verilog Types	p. 163
7.1.2 Verilog Logic and Numeric Values	p. 167
7.1.3 Specifying Values	p. 169
7.1.4 Verilog HDL Primitive Gates	p. 170
7.2 Operators and Expressions	p. 172
7.3 Example Illustrating the Use of Verilog HDL Operators: Hamming Code Encoder	p. 185
7.3.1 Simulating the Hamming Encoder	p. 188
References	p. 195
8 Describing Combinational and Sequential Logic using Verilog HDL	p. 197
8.1 The Data-Flow Style of Description: Review of the Continuous Assignment	p. 197
8.2 The Behavioural Style of Description: the Sequential Block	p. 198
8.3 Assignments within Sequential Blocks: Blocking and Nonblocking	p. 204
8.3.1 Sequential Statements	p. 204
8.4 Describing Combinational Logic using a Sequential Block	p. 209
8.5 Describing Sequential Logic using a Sequential Block	p. 217
8.6 Describing Memories	p. 229
8.7 Describing Finite-State Machines	p. 240
8.7.1 Example 1: Chess Clock Controller Finite-State Machine	p. 245
8.7.2 Example 2: Combination Lock Finite-State Machine with Automatic Lock Feature	p. 252
References	p. 265
9 Asynchronous Finite-State Machines	p. 267
9.1 Introduction	p. 267
9.2 Development of Event-Driven Logic	p. 269
9.3 Using the Sequential Equation to Synthesize an Event Finite-State Machine	p. 272
9.3.1 Short-cut Rule	p. 275
9.4 Implementing the Design using Sum of Product as used in a Programmable Logic Device	p. 276
9.4.1 Dropping the Present State n and Next State n + 1 Notation	p. 277
9.5 Development of an Event Version of the Single-Pulse Generator with Memory Finite-State Machine	p. 277
9.6 Another Event Finite-State Machine Design from Specification through to Simulation	p. 280
9.6.1 Important Note!	p. 280
9.6.2 A Motor Controller with Fault Current Monitoring	p. 281
9.7 The Hover Mower Finite-State Machine	p. 285
9.7.1 The Specification and a Possible Solution	p. 285
9.8 An Example with a Transition without any Input	p. 289
9.9 Unusual Example: Responding to a Microprocessor-Addressed Location	p. 291
9.10 An Example that uses a Mealy Output	p. 293
9.10.1 Tank Water Level Control System with Solutions	p. 293
9.11 An Example using a Relay Circuit	p. 296
9.12 Race Conditions in an Event Finite-State Machine	p. 299
9.12.1 Race between Primary Inputs	p. 300
9.12.2 Race between Secondary State Variables	p. 300
9.12.3 Race between Primary and Secondary Variables	p. 300
9.13 Wait-State Generator for a Microprocessor System	p. 301
9.14 Development of an Asynchronous Finite-State Machine for a Clothes Spinner System	p. 304
9.15 Caution when using Two-Way Branches	p. 309
9.16 Summary	p. 312
References	p. 312
10 Introduction to Petri Nets	p. 313
10.1 Introduction to Simple Petri Nets	p. 313
10.2 Simple Sequential Example using a Petri Net	p. 318
10.3 Parallel Petri Nets	p. 319
10.3.1 Another Example of a Parallel Petri Net	p. 323
10.4 Synchronizing Flow in a Parallel Petri Net	p. 324
10.4.1 Enabling and Disabling Arcs	p. 325
10.5 Synchronization of Two Petri Nets using Enabling and Disabling Arcs	p. 326
10.6 Control of a Shared Resource	p. 327
10.7 A Serial Receiver of Binary Data	p. 329
10.7.1 Equations for the First Petri Net	p. 333
10.7.2 Output	p. 333
10.7.3 Equations for the Main Petri Net	p. 333
10.7.4 Outputs	p. 333
10.7.5 The Shift Register	p. 334
10.7.6 Equations for the Shift Register	p. 334
10.7.7 The Divide-by-11 Counter	p. 335
10.7.8 The Data Latch	p. 335
10.8 Summary	p. 336
References	p. 336
Appendix A Logic Gates and Boolean Algebra Used in the Book	p. 337
A.1 Basic Gate Symbols Used in the Book with Boolean Equations	p. 337
A.2 The Exclusive OR and Exclusive NOR	p. 338
A.3 Laws of Boolean Algebra	p. 338
A.3.1 Basic OR Rules	p. 339
A.3.2 Basic AND Rules	p. 339
A.3.3 Associative and Commutative Laws	p. 340
A.3.4 Distributive Laws	p. 340
A.3.5 Auxiliary Law for Static 1 Hazard Removal	p. 341
A.3.5.1 Proof of Auxiliary Rule	p. 341
A.3.6 Consensus Theorem	p. 342
A.3.7 The Effect of Signal Delay in Logic Gates	p. 343
A.3.8 De Morgan's Theorem	p. 343
A.4 Examples of Applying the Laws of Boolean Algebra	p. 345
A.4.1 Example: Converting AND-OR to NAND	p. 345
A.4.2 Example: Converting AND-OR to NOR	p. 345
A.4.3 Logical Adjacency Rule	p. 345
A.5 Summary	p. 346
Appendix B Counting and Shifting Circuit Techniques	p. 347
B.1 Basic Up and Down Synchronous Binary Counter Development	p. 347
B.2 Example for a 4-Bit Synchronous Up-Counter Using T-Type Flip-Flops	p. 349
B.3 Parallel-Loading Counters: Using T Flip-Flops	p. 352
B.4 Using D Flip-Flops to Build Parallel-Loading Counters with Cheap Programmable Logic Devices	p. 353
B.5 Simple Binary Up-Counter: with Parallel Inputs	p. 354
B.6 Clock Circuit to Drive the Counter (And Finite-State Machines)	p. 355
B.7 Counter Design using Don't Care States	p. 355
B.8 Shift Registers	p. 357
B.9 Asynchronous Receiver Details of Chapter 4	p. 358
B.9.1 The 11-Bit Shift Registers for the Asynchronous Receiver Module	p. 360
B.9.2 Divide-by-11 Counter	p. 362
B.9.3 Complete Simulation of the Asynchronous Receiver Module of Chapter 4	p. 364
B.10 Summary	p. 365
Appendix C Tutorial on the Use of Verilog HDL to Simulate a Finite-State Machine Design	p. 367
C.1 Introduction	p. 367
C.2 The Single Pulse with Memory Synchronous Finite-State Machine Design: Using Verilog HDL to Simulate	p. 367
C.2.1 Specification	p. 367
C.2.2 Block Diagram	p. 367
C.2.3 State Diagram	p. 368
C.2.4 Equations from the State Diagram	p. 368
C.2.5 Translation into a Verilog Description	p. 369
C.3 Test-Bench Module and its Purpose	p. 372
C.4 Using SynaptiCAD's VeriLogger Extreme Simulator	p. 376
C.5 Summary	p. 378
Appendix D Implementing State Machines using Verilog Behavioural Mode	p. 379
D.1 Introduction	p. 379
D.2 The Single-Pulse/Multiple-Pulse Generator with Memory Finite-State Machine Revisited	p. 379
D.3 The Memory Tester Finite-State Machine in Section 5.6	p. 383
D.4 Summary	p. 386
Index	p. 387

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