System-on-a-chip : design and test

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Title:

Personal Author:

Rajsuman, Rochit

Publication Information:

Boston, MA : Artech House, 2000

ISBN:

9781580531078

Subject Term:

Embedded computer systems -- Design and construction

Embedded computer systems -- Testing

Application specific integrated circuits -- Design and construction

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Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010099163	TK7895.E42 R34 2000	Open Access Book	Book	Searching... Unknown

Starting with a basic overview of system-on-a-chip (SoC) including definitions of related terms, this text explains SoC design challenges, together with developments in SoC design and and test methodologies.

Author Notes

Rochit Rajsuman received his B.Tech. in Electrical Engineering from K.N. Institute of Technology, India, his M.S. in Electrical Engineering from the University of Oklahoma, and his Ph.D. in Electrical Engineering from Colorado State University.

Rajsuman manages test research at Advantest America R & D Center in Santa Clara, California. He is a senior member of the IEEE and a Golden Core member of the Computer Society.

050

Preface	p. xi
Acknowledgment	p. xiii
Part I Design	p. 1
1 Introduction	p. 3
1.1 Architecture of the Present-Day SoC	p. 5
1.2 Design Issues of SoC	p. 8
1.3 Hardware-Software Codesign	p. 14
1.3.1 Codesign Flow	p. 15
1.3.2 Codesign Tools	p. 18
1.4 Core Libraries, EDA Tools, and Web Pointers	p. 21
1.4.1 Core Libraries	p. 21
1.4.2 EDA Tools and Vendors	p. 23
1.4.3 Web Pointers	p. 28
References	p. 29
2 Design Methodology for Logic Cores	p. 33
2.1 SoC Design Flow	p. 34
2.2 General Guidelines for Design Reuse	p. 36
2.2.1 Synchronous Design	p. 36
2.2.2 Memory and Mixed-Signal Design	p. 36
2.2.3 On-Chip Buses	p. 38
2.2.4 Clock Distribution	p. 39
2.2.5 Clear/Set/Reset Signals	p. 40
2.2.6 Physical Design	p. 40
2.2.7 Deliverable Models	p. 42
2.3 Design Process for Soft and Firm Cores	p. 43
2.3.1 Design Flow	p. 43
2.3.2 Development Process for Soft/Firm Cores	p. 45
2.3.3 RTL Guidelines	p. 46
2.3.4 Soft/Firm Cores Productization	p. 47
2.4 Design Process for Hard Cores	p. 47
2.4.1 Unique Design Issues in Hard Cores	p. 47
2.4.2 Development Process for Hard Cores	p. 49
2.5 Sign-Off Checklist and Deliverables	p. 51
2.5.1 Sign-Off Checklist	p. 51
2.5.2 Soft Core Deliverables	p. 52
2.5.3 Hard Core Deliverables	p. 53
2.6 System Integration	p. 53
2.6.1 Designing With Hard Cores	p. 53
2.6.2 Designing With Soft Cores	p. 54
2.6.3 System Verification	p. 54
References	p. 55
3 Design Methodology for Memory and Analog Cores	p. 57
3.1 Why Large Embedded Memories	p. 57
3.2 Design Methodology for Embedded Memories	p. 59
3.2.1 Circuit Techniques	p. 61
3.2.2 Memory Compiler	p. 66
3.2.3 Simulation Models	p. 70
3.3 Specifications of Analog Circuits	p. 72
3.3.1 Analog-to-Digital Converter	p. 72
3.3.2 Digital-to-Analog Converter	p. 75
3.3.3 Phase-Locked Loops	p. 78
3.4 High-Speed Circuits	p. 79
3.4.1 Rambus ASIC Cell	p. 79
3.4.2 IEEE 1394 Serial Bus (Firewire) PHY Layer	p. 80
3.4.3 High-Speed I/O	p. 81
References	p. 81
4 Design Validation	p. 85
4.1 Core-Level Validation	p. 86
4.1.1 Core Validation Plan	p. 86
4.1.2 Testbenches	p. 88
4.1.3 Core-Level Timing Verification	p. 90
4.2 Core Interface Verification	p. 93
4.2.1 Protocol Verification	p. 94
4.2.2 Gate-Level Simulation	p. 95
4.3 SoC Design Validation	p. 95
4.3.1 Cosimulation	p. 97
4.3.2 Emulation	p. 101
4.3.3 Hardware Prototypes	p. 101
Reference	p. 103
5 Core and SoC Design Examples	p. 105
5.1 Microprocessor Cores	p. 105
5.1.1 V830R/AV Superscaler RISC Core	p. 109
5.1.2 Design of PowerPC 603e G2 Core	p. 110
5.2 Comments on Memory Core Generators	p. 112
5.3 Core Integration and On-Chip Bus	p. 113
5.4 Examples of SoC	p. 115
5.4.1 Media Processors	p. 116
5.4.2 Testability of Set-Top Box SoC	p. 121
References	p. 122
Part II Test	p. 123
6 Testing of Digital Logic Cores	p. 125
6.1 SoC Test Issues	p. 126
6.2 Access, Control, and Isolation	p. 128
6.3 IEEE P1500 Effort	p. 129
6.3.1 Cores Without Boundary Scan	p. 132
6.3.2 Core Test Language	p. 135
6.3.3 Cores With Boundary Scan	p. 135
6.4 Core Test and IP Protection	p. 138
6.5 Test Methodology for Design Reuse	p. 142
6.5.1 Guidelines for Core Testability	p. 142
6.5.2 High-Level Test Synthesis	p. 143
6.6 Testing of Microprocessor Cores	p. 144
6.6.1 Built-in Self-Test Method	p. 144
6.6.2 Example: Testability Features of ARM Processor Core	p. 147
6.6.3 Debug Support for Microprocessor Cores	p. 150
References	p. 152
7 Testing of Embedded Memories	p. 155
7.1 Memory Fault Models and Test Algorithms	p. 156
7.1.1 Fault Models	p. 156
7.1.2 Test Algorithms	p. 157
7.1.3 Effectiveness of Test Algorithms	p. 160
7.1.4 Modification With Multiple Data Background	p. 161
7.1.5 Modification for Multiport Memories	p. 161
7.1.6 Algorithm for Double-Buffered Memories	p. 161
7.2 Test Methods for Embedded Memories	p. 162
7.2.1 Testing Through ASIC Functional Test	p. 163
7.2.2 Test Application by Direct Access	p. 164
7.2.3 Test Application by Scan or Collar Register	p. 164
7.2.4 Memory Built-in Self-Test	p. 164
7.2.5 Testing by On-Chip Microprocessor	p. 169
7.2.6 Summary of Test Methods for Embedded Memories	p. 171
7.3 Memory Redundancy and Repair	p. 171
7.3.1 Hard Repair	p. 171
7.3.2 Soft Repair	p. 175
7.4 Error Detection and Correction Codes	p. 175
7.5 Production Testing of SoC With Large Embedded Memory	p. 176
References	p. 177
8 Testing of Analog and Mixed-Signal Cores	p. 181
8.1 Analog Parameters and Characterization	p. 182
8.1.1 Digital-to-Analog Converter	p. 182
8.1.2 Analog-to-Digital Converter	p. 184
8.1.3 Phase-Locked Loop	p. 188
8.2 Design-for-Test and Built-in Self-Test Methods for Analog Cores	p. 191
8.2.1 Fluence Technology's Analog BIST	p. 192
8.2.2 LogicVision's Analog BIST	p. 192
8.2.3 Testing by On-Chip Microprocessor	p. 195
8.2.4 IEEE P1149.4	p. 197
8.3 Testing of Specific Analog Circuits	p. 200
8.3.1 Rambus ASIC Cell	p. 200
8.3.2 Testing of 1394 Serial Bus/Firewire	p. 201
References	p. 204
9 Iddq Testing	p. 207
9.1 Physical Defects	p. 207
9.1.1 Bridging (Shorts)	p. 208
9.1.2 Gate-Oxide Defects	p. 212
9.1.3 Open (Breaks)	p. 213
9.1.4 Effectiveness of Iddq Testing	p. 215
9.2 Iddq Testing Difficulties in SoC	p. 218
9.3 Design-for-Iddq-Testing	p. 224
9.4 Design Rules for Iddq Testing	p. 228
9.5 Iddq Test Vector Generation	p. 230
References	p. 234
10 Production Testing	p. 239
10.1 Production Test Flow	p. 239
10.2 At-Speed Testing	p. 241
10.2.1 RTD and Dead Cycles	p. 241
10.2.2 Fly-By	p. 243
10.2.3 Speed Binning	p. 245
10.3 Production Throughput and Material Handling	p. 246
10.3.1 Test Logistics	p. 246
10.3.2 Tester Setup	p. 247
10.3.3 Multi-DUT Testing	p. 248
References	p. 249
11 Summary and Conclusions	p. 251
11.1 Summary	p. 251
11.2 Future Scenarios	p. 254
Appendix RTL Guidelines for Design Reuse	p. 257
A.1 Naming Convention	p. 257
A.2 General Coding Guidelines	p. 258
A.3 RTL Development for Synthesis	p. 260
A.4 RTL Checks	p. 262
About the Author	p. 265
Index	p. 267

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Table of Contents