High performance ASIC design : using synthesizable domino logic in an ASIC flow

Presenting a methodology for using domino logic in an ASIC design flow developed over several years in an industrial context, this text covers practical issues related to the use of domino logic in an automated framework, and brings together all the knowledge needed to apply these design techniques in practice. Beginning with a discussion of how to achieve high speed in ASIC designs, subsequent chapters detail the design and characterization of standard cell compatible domino logic libraries and an advanced domino logic synthesis flow. The results achieved by using automated domino logic design techniques, including silicon measurements, are used to validate the presented solution. With design examples including the implementation of the execution unit of a microprocessor and a Viterbi decoder, this text is ideal for graduate students and researchers in electrical and computer engineering and also for circuit designers in industry.

Author Notes

Razak Hossain is a Senior Principal Engineer at STMicroelectonics Inc., San Diego, California

Preface	p. vii
Abbreviations	p. ix
1 An introduction to domino logic	p. 1
1.1 CMOS and NMOS	p. 1
1.2 Domino logic circuits	p. 5
1.3 Clocking domino logic	p. 12
1.4 Summary	p. 15
2 High-speed digital design	p. 18
2.1 Microprocessors since 1989	p. 18
2.2 Microarchitectures for high speed	p. 22
2.3 Designing and using high-speed memories	p. 31
2.4 What to remember if applying domino logic	p. 35
3 Domino logic library design	p. 37
3.1 High-speed digital circuit design	p. 37
3.2 An introduction to standard cells	p. 42
3.3 Designing a high-performance standard cell library	p. 45
3.4 Circuit design of domino logic cells: a qualitative approach	p. 48
3.5 Circuit design of domino logic cells: a quantitative approach	p. 51
3.6 Characterizing domino logic-compatible registers	p. 63
3.7 Layout of domino logic standard cells	p. 65
3.8 Timing models for domino logic cells	p. 66
4 Domino logic synthesis	p. 70
4.1 Introduction to domino logic synthesis	p. 70
4.2 Unate transform	p. 73
4.3 Phase assignment	p. 75
4.4 Phase-assignment rules	p. 77
4.5 An example domino synthesis flow	p. 86
4.6 Schematic capture of domino designs	p. 106
5 Circuits designed with domino logic in an ASIC flow	p. 108
5.1 Introduction	p. 108
5.2 Domino integer execution unit	p. 108
5.3 A synthesized domino logic DSP core	p. 119
5.4 A synthesizable domino logic Viterbi add-compare-select (ACS) test chip	p. 121
5.5 Intel's published domino logic synthesis flow	p. 124
5.6 Conclusions	p. 126
6 Evolution of domino logic synthesis	p. 127
6.1 The state of digital ASIC design methodologies	p. 127
6.2 Process trends and domino logic	p. 128
6.3 Clocking methodology for domino circuits	p. 130
6.4 Synthesizing other dynamic logic families	p. 132
6.5 Flow improvements for domino synthesis	p. 137
6.6 The case for domino logic synthesis	p. 141
Index	p. 143

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Author Notes

Table of Contents