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Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
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Searching... | 30000010251054 | TK7874.65 W654 2009 | Open Access Book | Book | Searching... |
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Summary
Summary
The Number 1 VLSI Design Guide--Now Fully Updated for IP-Based Design and the Newest Technologies
Modern VLSI Design, Fourth Edition , offers authoritative, up-to-the-minute guidance for the entire VLSI design process--from architecture and logic design through layout and packaging. Wayne Wolf has systematically updated his award-winning book for today's newest technologies and highest-value design techniques. Wolf introduces powerful new IP-based design techniques at all three levels: gates, subsystems, and architecture. He presents deeper coverage of logic design fundamentals, clocking and timing, and much more. No other VLSI guide presents as much up-to-date information for maximizing performance, minimizing power utilization, and achieving rapid design turnarounds.
Coverage includes 
All-new material on IP-based design Extensive new coverage of networks-on-chips New coverage of using FPGA fabrics to improve design flexibility New material on image sensors, busses, Rent's Rule, pipelining, and more Updated VLSI technology parameters reflecting the latest advances Revised descriptions of HDLs and other VLSI design tools Advanced techniques for overcoming bottlenecks and reducing crosstalk Low-power design techniques for enhancing reliability and extending battery life Testing solutions for every level of abstraction, from gates to architecture Revamped end-of-chapter problems that fully reflect today's VLSI design challenges Wolf introduces a top-down, systematic design methodology that begins with high-level models, extends from circuits to architecture, and facilitates effective testing. Along the way, he brings together all the skills VLSI design professionals will need to create tomorrow's state-of-the-art devices.
Author Notes
Wayne Wolf is Rhesa "Ray" S. Farmer Jr. Distinguished Chair in Embedded Computing Systems and Georgia Research Alliance Eminent Scholar at the Georgia Institute of Technology. Before joining Georgia Tech, he was with Princeton University from 1989 to 2007 and AT&T Bell Laboratories from 1984 to 1989. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University in 1980, 1981, and 1984, respectively. His research interests include VLSI systems, embedded computing, cyber-physical systems, and embedded computer vision. He has chaired several conferences, including CODES, EMSOFT, CASES, and ICCD. He was founding editor-in-chief of ACM Transactions on Embedded Computing Systems and founding co-editor-in-chief of Design Automation for Embedded Systems . He is a Fellow of the ACM and IEEE. He received the ASEE/CSE and HP Frederick E. Terman Award in 2003 and the IEEE Circuits and Systems Education Award in 2006.
Excerpts
Excerpts
I have set up a new Web site for my books. You can find it at http://www.waynewolf.us or through my Georgia Tech home page. I set for myself two goals in producing this fourth edition of Modern VLSI Design . First, I wanted to update the book for more modern technologies and design methods. This includes obvious changes like smaller design rules. But it also includes emphasizing more system-level topics such as IP-based design. Second, I wanted to continue to improve the book's treatment of the fundamentals of logic design. VLSI is often treated as circuit design, meaning that traditional logic design topics like pipelining can easily become lost. In between the third and fourth editions of this book, I respun the third edition as FPGA-Based System Design . That book added new FPGA-oriented material to material from Modern VLSI Design . In this edition, I've decided to borrow back some material from the FPGA book. The largest inclusion was the section on sequential system performance. I had never been happy with my treatment of that material. After 10 years of trying, I came up with a more acceptable description of clocking and timing in the FPGA book and I am now bringing it back to VLSI. I included material on busses, Rent's Rule, pipelining, and hardware description languages. I also borrowed some material on FPGAs themselves to flesh out that treatment from the third edition. An increasing number of designs include FPGA fabrics to add flexibility; FPGAs also make good design projects for VLSI classes. Material on IP-based design is presented at several levels of hierarchy: gates, subsystems, and architecture. As part of this update, I eliminated the CAD chapter from this edition because I finally decided that such detailed treatment of many of the CAD tools is not strictly necessary. I also deleted the chapter on chip design. Chip design has changed fundamentally in the past 20 years since I started to work on this book. Chip designers think less about rectangles and more about large blocks. To reflect this shift, I added a new chapter on system-on-chip design. Intellectual property is a fundamental fact of life in VLSI design--either you will design IP modules or you will use someone else's IP modules. In addition to changing the chapters themselves, I also substantially revised the problems at the end of each chapter. These new problems better reflect the new material and they provide new challenges for students. While I was at it, I also made some cosmetic changes to the book. I changed the typesetting to use the same format for left- and right-hand pages, an unfortunate necessity with today's tools. I also added margin headers--those phrases you see on the left-hand margin. Wayne Wolf Atlanta, Georgia Excerpted from Modern VLSI Design: IP-Based Design by Wayne Wolf All rights reserved by the original copyright owners. Excerpts are provided for display purposes only and may not be reproduced, reprinted or distributed without the written permission of the publisher.Table of Contents
Preface to the Fourth Edition | p. xv |
Preface to the Third Edition | p. xvii |
Preface to the Second Edition | p. xviii |
Preface | p. xix |
About the Author | p. xxii |
Chapter 1 Digital Systems and VLSI | p. 1 |
1.1 Why Design Integrated Circuits? | p. 3 |
1.2 Integrated Circuit Manufacturing | p. 5 |
1.3 CMOS Technology | p. 18 |
1.4 Integrated Circuit Design Techniques | p. 21 |
1.5 IP-Based Design | p. 33 |
1.6 A Look into the Future | p. 40 |
1.7 Summary | p. 41 |
1.8 References | p. 42 |
1.9 Problems | p. 42 |
Chapter 2 Fabrication and Devices | p. 43 |
2.1 Introduction | p. 45 |
2.2 Fabrication Processes | p. 45 |
2.3 Transistors | p. 52 |
2.4 Wires and Vias | p. 73 |
2.5 Fabrication Theory and Practice | p. 84 |
2.6 Reliability | p. 98 |
2.7 Layout Design and Tools | p. 103 |
2.8 References | p. 119 |
2.9 Problems | p. 120 |
Chapter 3 Logic Gates | p. 123 |
3.1 Introduction | p. 125 |
3.2 Combinational Logic Functions | p. 125 |
3.3 Static Complementary Gates | p. 128 |
3.4 Switch Logic | p. 157 |
3.5 Alternative Gate Circuits | p. 159 |
3.6 Low-Power Gates | p. 169 |
3.7 Delay through Resistive Interconnect | p. 175 |
3.8 Delay through Inductive Interconnect | p. 187 |
3.9 Design-for-Yield | p. 193 |
3.10 Gates as IP | p. 195 |
3.11 References | p. 198 |
3.12 Problems | p. 199 |
Chapter 4 Combinational Logic Networks | p. 205 |
4.1 Introduction | p. 207 |
4.2 Standard Cell-Based Layout | p. 207 |
4.3 Combinational Network Delay | p. 219 |
4.4 Logic and Interconnect Design | p. 235 |
4.5 Power Optimization | p. 246 |
4.6 Switch Logic Networks | p. 251 |
4.7 Combinational Logic Testing | p. 255 |
4.8 References | p. 262 |
4.9 Problems | p. 262 |
Chapter 5 Sequential Machines | p. 267 |
5.1 Introduction | p. 269 |
5.2 Latches and Flip-Flops | p. 269 |
5.3 Sequential Systems and Clocking Disciplines | p. 281 |
5.4 Performance Analysis | p. 292 |
5.5 Clock Generation | p. 310 |
5.6 Sequential System Design | p. 312 |
5.7 Power Optimization | p. 329 |
5.8 Design Validation | p. 330 |
5.9 Sequential Testing | p. 332 |
5.10 References | p. 340 |
5.11 Problems | p. 340 |
Chapter 6 Subsystem Design | p. 345 |
6.1 Introduction | p. 347 |
6.2 Combinational Shifters | p. 349 |
6.3 Adders | p. 352 |
6.4 ALUs | p. 360 |
6.5 Multipliers | p. 360 |
6.6 High-Density Memory | p. 369 |
6.7 Image Sensors | p. 382 |
6.8 Field-Programmable Gate Arrays | p. 385 |
6.9 Programmable Logic Arrays | p. 387 |
6.10 Buses and Networks-on-Chis | p. 391 |
6.11 Data Paths | p. 415 |
6.12 Subsystems as IP | p. 417 |
6.13 References | p. 422 |
6.14 Problems | p. 422 |
Chapter 7 Floorplanning | p. 425 |
7.1 Introduction | p. 427 |
7.2 Floorplanning Methods | p. 427 |
7.3 Global Interconnect | p. 439 |
7.4 Floorplan Design | p. 450 |
7.5 Off-Chip Connections | p. 452 |
7.6 References | p. 461 |
7.7 Problems | p. 462 |
Chapter 8 Architecture Design | p. 471 |
8.1 Introduction | p. 473 |
8.2 Hardware Description Languages | p. 473 |
8.3 Register-Transfer Design | p. 495 |
8.4 Pipelining | p. 509 |
8.5 High-Level Synthesis | p. 518 |
8.6 Architectures for Low Power | p. 539 |
8.7 GALS Systems | p. 544 |
8.8 Architecture Testing | p. 545 |
8.9 IP Components | p. 550 |
8.10 Design Methodologies | p. 551 |
8.11 Multiprocessor System-on-Chip Design | p. 559 |
8.12 References | p. 565 |
8.13 Problems | p. 565 |
Appendix A A Chip Designer's Lexicon | p. 571 |
Appendix B Hardware Description Languages | p. 589 |
B.1 Introduction | p. 589 |
B.2 Verilog | p. 589 |
B.3 VHDL | p. 594 |
References | p. 599 |
Index | p. 613 |