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1. 
Cover image for VLSI design of fast pipelined discrete cosine transform
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Cover image for VLSI design of fast pipelined discrete cosine transform
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Cover image for Bio/CMOS interfaces and co-design
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Cover image for Advanced model order reduction techniques in VLSI design
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Cover image for VLSI test principles and architectures : design for testability
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Cover image for Design & implementation (VLSI) of an all digital phase locked loop (ADPLL)