Continuous-time sigma-delta A/D conversion : fundamentals, performance limits and robust implementations

Sigma-delta A/D converters are a key building block in wireless and multimedia applications. This comprehensive book deals with all relevant aspects arising during the analysis, design and simulation of the now widespread continuous-time implementations of sigma-delta modulators. The results of several years of research by the authors in the field of CT sigma-delta modulators are covered, including the analysis and modeling of different CT modulator architectures, CT/DT loop filter synthesis, a detailed error analysis of all components, and possible compensation/correction schemes for the non-ideal behavior in CT sigma-delta modulators. Guidance for obtaining low-power consumption and several practical implementations are also presented. It is shown that all the proposed new theories, architectures and possible correction techniques have been confirmed by measurements on discrete or integrated circuits. Quantitative results are also provided, thus enabling prediction of the resulting accuracy.

Author Notes

Maurits Ortmanns received the Dipl.-Ing. (M.Sc.) degree in electrical engineering with highest honours from the Saarland University, Saarbruecken, Germany, in 1999. In 1997 and 1998, he was with the Research Center Karlsruhe, Germany, and with EXAR, Inc., Fremont, Ca, as a student research assistant. In 1999, Mr. Ortmanns joined the Institute of Microelectronics of the Saarland University, where he started to work towards the Ph.D. degree in the field of continuous-time sigma-delta modulator design. In 2002, he moved to the Institute of Microsystem Technology, Albert-Ludwigs-University, Freiburg, Germany. Since April 2004, Mr. Ortmanns is with SCI-Worx GmbH, Hannover, Germany, where he is working in the field of RF analog circuits. His main research interests include microelectronics, microsensors and biosensors. Mr. Ortmanns is member of the German National Academic Foundation.

1 Introduction	p. 1
1.1 Motivation and History	p. 1
1.2 Intention of this Work	p. 3
1.3 Further Recommended Literature	p. 3
1.4 Organization of this Book	p. 5
2 Basic Understanding of [Sigma][Delta] A/D Conversion	p. 7
2.1 Basics of A/D Conversion	p. 7
2.1.1 Sampling and Quantization	p. 7
2.1.2 Quantizer White Noise Model	p. 10
2.2 Performance Metrics	p. 11
2.2.1 Frequency Domain Metrics	p. 12
2.2.2 Noise and Power Metrics	p. 13
2.2.3 Used Tools and Program Code	p. 15
2.3 Performance of Nyquist Rate Converters	p. 16
2.4 Performance of Oversampled Converters	p. 17
2.5 Oversampled Noise-Shaping Converters: [Sigma][Delta] ADC	p. 18
2.5.1 The First-Order [Sigma][Delta] Modulator	p. 20
2.5.2 Pattern-Noise and Dithering in [Sigma][Delta] Modulators	p. 21
2.6 Performance Increase in [Sigma][Delta] Modulators	p. 22
2.6.1 High OSR [Sigma][Delta] Modulators	p. 23
2.6.2 Higher Order [Sigma][Delta] Modulators	p. 23
2.6.3 Multibit [Sigma][Delta] Modulators	p. 24
2.7 Single-Loop, Single-Bit, Higher Order [Sigma][Delta] Modulators	p. 25
2.7.1 Distributed Feedback Topology	p. 25
2.7.2 Feed-Forward Topology	p. 27
2.7.3 Local Feedback Loops	p. 28
2.7.4 [Sigma][Delta] Modulator Loop Filter Stability and Scaling	p. 29
2.7.5 Effective Quantizer Gain in [Sigma][Delta] Modulators	p. 32
2.8 Multiloop, Cascaded [Sigma][Delta] Modulators	p. 33
2.9 Specialized Architectures	p. 36
2.10 Loop Filters with Bandpass Characteristic	p. 37
3 Continuous-Time [Sigma][Delta] Modulators	p. 39
3.1 CT [Sigma][Delta] Modulator Issues	p. 39
3.1.1 Sampling Operation	p. 40
3.1.2 Filter Realization	p. 41
3.1.3 Quantizer Realization	p. 42
3.1.4 Feedback Realization	p. 43
3.1.5 DT/CT Modulators Trade-offs	p. 47
3.2 DT-to-CT Conversion of [Sigma][Delta] Modulators	p. 47
3.2.1 The Impulse-Invariant Transformation	p. 48
3.2.2 Modified Z-Transform	p. 52
3.2.3 Differences of the Two Transformations	p. 54
3.2.4 DT-to-CT Conversion of Cascaded [Sigma][Delta] Modulators	p. 55
3.3 Direct Filter Synthesis	p. 61
3.4 STF and NTF in CT [Sigma][Delta] Modulators	p. 63
3.5 Implicit Antialiasing Filter in CT [Sigma][Delta] Modulators	p. 65
3.5.1 Implicit AAF of the CT Third-Order Modulator	p. 66
3.5.2 Implicit AAF of the CT SOFO Modulator	p. 69
3.6 Calculations with the CT Loop Filters	p. 71
3.7 Alternatives for CT Filter Implementation	p. 71
3.7.1 gmC-Integrator	p. 71
3.7.2 LC-Resonator	p. 73
3.7.3 Active gmC-Integrator	p. 74
3.7.4 Current-mode Integrator	p. 75
3.7.5 Log-Domain Integrator	p. 75
3.7.6 Active RC-Integrator	p. 76
3.7.7 Active MOSFET-C-Integrator	p. 77
3.7.8 Conclusion on the Commonly Used CT Integrators	p. 77
3.8 Classification of Non-Idealities in CT [Sigma][Delta] Modulators	p. 78
3.8.1 Input Referred Errors	p. 81
3.8.2 Organization of the Following Chapters	p. 83
4 DAC Nonidealities in Continuous-Time [Sigma][Delta] Modulators	p. 85
4.1 Feedback DAC Error Classification	p. 85
4.2 Excess Loop Delay in Continuous-Time [Sigma][Delta] Modulators	p. 85
4.2.1 Coefficient Mismatch through Excess Loop Delay	p. 86
4.2.2 Increased Modulator Order through Excess Loop Delay	p. 87
4.2.3 Alternative Approach to the Effect of Excess Loop Delay	p. 88
4.2.4 Compensation for Excess Loop Delay in CT [Sigma][Delta] Modulators	p. 89
4.2.5 Simulation Results on Excess Loop Delay	p. 92
4.2.6 Extension to Other Architectures	p. 94
4.3 Clock Jitter in Continuous-Time [Sigma][Delta] Modulators	p. 94
4.3.1 Jitter Effects in CT [Sigma][Delta] Modulators	p. 94
4.3.2 Calculation of the Jitter Influence for Rectangular Feedback	p. 96
4.3.3 Reduction of Clock Jitter Influence Using Multibit DACs	p. 99
4.3.4 Reduction of Clock Jitter Influence Using Shaped Feedback Waveform DACs	p. 100
4.3.5 Further Possibilities for CT [Sigma][Delta] Modulators with Reduced Clock Jitter Sensitivity	p. 106
4.3.6 CT Loop Filters Employing Shaped Feedback Waveforms	p. 107
4.3.7 Trade-off for Reduced Clock Jitter Sensitivity	p. 108
4.3.8 Discussion on the White Clock Jitter Model	p. 109
4.3.9 Simulation Results on Clock Jitter	p. 110
4.4 DAC Slew Rate Limitation	p. 113
4.5 DAC Nonlinearity	p. 114
5 Filter Nonidealities in Continuous-Time [Sigma][Delta] Modulators	p. 117
5.1 Analytical Description	p. 117
5.1.1 Analytical Description of the Nonideal CT Filter Behavior	p. 117
5.1.2 Quantitative Impact of Nonideal CT Filter Behavior	p. 118
5.2 Finite OpAmp Gain	p. 119
5.2.1 Simulation Results	p. 121
5.3 Integrator Gain or Time-Constant Error	p. 121
5.3.1 Effective Quantizer Gain and Integrator Gain Errors	p. 122
5.3.2 Single-Loop Modulators	p. 123
5.3.3 Cascaded Modulators	p. 124
5.3.4 Simulation Results	p. 125
5.3.5 Compensation of Gain Errors in Single-Loop [Sigma][Delta] Modulators	p. 126
5.3.6 Compensation of Gain Errors in Cascaded [Sigma][Delta] Modulators	p. 126
5.4 Finite Amplifier Gain-Bandwidth Product	p. 128
5.4.1 Basic Analytical Description of Finite GBW	p. 129
5.4.2 Extended Model for Single-Loop Modulators	p. 131
5.4.3 Compensation for Finite GBW-Induced Errors in CT [Sigma][Delta] Modulators	p. 134
5.4.4 Influence on Different Feedback Implementations	p. 139
5.5 Finite Amplifier Slew Rate	p. 141
5.5.1 Slew Rate in CT [Sigma][Delta] Modulators	p. 141
5.5.2 Influence of Different Feedback Waveforms and [Sigma][Delta] Architectures	p. 142
5.5.3 Simulation Results	p. 143
5.6 Other Integrator Nonidealities	p. 146
5.6.1 Limited Output Swing	p. 146
5.6.2 Circuit Noise	p. 147
5.6.3 Integrator Nonlinearity	p. 150
6 Quantizer Nonidealities in Continuous-Time [Sigma][Delta] Modulators	p. 155
7 CT [Sigma][Delta] Modulator Design Examples	p. 157
7.1 FOM Based Design Strategy for CT [Sigma][Delta] Modulators	p. 157
7.1.1 Generic Figure of Merit Calculation	p. 158
7.1.2 Single-Loop Architectures	p. 160
7.1.3 Multibit Single-Loop Architectures	p. 161
7.1.4 Cascaded Architectures	p. 162
7.1.5 FOM Based Design Example: A 12-Bit 25 kHz [Sigma][Delta] Modulator	p. 163
7.1.6 Expansion Features of the FOM Based Design Strategy	p. 164
7.2 Low-Power Limits in Analog Circuits	p. 165
7.2.1 Low-Power Limits in Noise-Dominated Circuits	p. 165
7.2.2 Low-Power Limits in Noise-Dominated and Distortion-Dominated Circuits	p. 166
7.2.3 Low-Power Limits in Matching-Dominated Circuits	p. 166
7.2.4 Low-Power Limits in [Sigma][Delta] Modulators	p. 167
7.3 Implementation Example I: A 12-Bit 25 kHz 1.5 V CT [Sigma][Delta] Modulator	p. 169
7.3.1 Loop Filter Design	p. 170
7.3.2 Circuit Blocks	p. 174
7.3.3 Modulator Design	p. 178
7.3.4 Measurements	p. 181
7.4 Implementation Example II: A CT [Sigma][Delta] Modulator with SCR-Feedback	p. 185
7.4.1 SCR-Feedback Implementation	p. 185
7.4.2 SCR Time Constant and Loop Filter Scaling	p. 186
7.4.3 Experimental Results	p. 188
7.4.4 CT [Sigma][Delta] Modulator with SCR-I-Feedback	p. 189
7.5 Implementation Example III: A 12-Bit 2 MHz 1 V CT [Sigma][Delta] Modulator	p. 191
7.5.1 Modulator Architecture	p. 191
7.5.2 Loop Filter	p. 192
7.5.3 Circuit Implementation	p. 195
7.5.4 Layout Consideration	p. 203
7.5.5 Experimental Results	p. 203
7.6 Implementation Example IV: A 2-1-1 Cascaded CT [Sigma][Delta] Modulator	p. 205
7.6.1 Circuit Realization of the Cascaded Modulator	p. 207
7.6.2 Measured Ideal Modulator Performance	p. 207
7.6.3 Verification of the Digital Gain-Error Cancellation	p. 209
A Program Code	p. 213
B General Loop Filter Pole Transformation for the Exponential Feedback	p. 215
C On the CT Integrator, Sampling Frequency fs and the Amplifier GBW	p. 217
References	p. 221
Index	p. 239

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