Digital integrated circuits : analysis and design

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Title:

Personal Author:

Ayers, John E

Publication Information:

Boca Raton, FL : CRC Press, 2004

ISBN:

9780849319518

Subject Term:

Digital integrated circuits -- Design and construction

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010125142	TK7874.65 A93 2004	Open Access Book	Book	Searching... Unknown

There is no field of enterprise today more dynamic or more challenging than Digital Integrated Circuits. But because of its rapid development, the field has quickly outgrown most of the standard textbooks. The field is also decidedly interdisciplinary. Engineers now must understand materials, physics, devices, processing electromagnetics, computer tools, and economics along with circuits and design rules, but few if any texts take the interdisciplinary approach that best prepares students for their future studies and practice.

Author John Ayers designed Digital Integrated Circuits: Analysis and Design to meet three primary objectives:

Take an interdisciplinary approach that will stay relevant for years to come
Provide broad coverage of the field relevant to students interested in designing integrated circuits and to those aiming towards designing with integrated circuits
Focus on the underlying principles rather than the details of current technologies that will soon be obsolete

Rich with pedagogical features and supplementary materials, this book appears destined to set a new standard for digital integrated circuits texts. It provides all of the materials you need to offer the best possible course for engineering or computer science students, and it's clear, systematic presentation and wealth of solved examples build the solid, practical foundation today's students need.

Prerequisites: Students will need an upper-level undergraduate engineering and science background with courses in circuits, electronics, and digital logic.

Author Notes

J.E. Ayers earned the M.S. EE in 1987 and the Ph.D. EE in 1990, both from Rensselaer Polytechnic Institute. Since then he has been employed in academic research and teaching at the University of Connecticut, Storrs

Reviews 1

Choice Review

Digital integrated circuits became interesting as a result of advances in semiconductor technology and miniaturization of components. Ayers (Univ. of Connecticut) focuses on principles underlying semiconductor technology such as bipolar and MOS concepts and the introduction of the computer-aided tool PSPICE in designing and simulating integrated circuits. Early chapters are devoted to a review of basic semiconductor materials and the physics necessary for understanding these integrated circuit components. Other chapters discuss simple bipolar transistor techniques ranging from transistor-transistor logic (TTL) and emitter-couple logic (ECL) to the more complex field effect transistor methods in metal-oxide field effect devices (MOSFET). Later chapters emphasize specialized integrated circuit devices and attempt to bring all the previously discussed techniques into the design of digital integrated circuits. Generally speaking, Ayers discusses a wide range of topics--each properly arranged, concisely explained, and clearly presented. He offers a learn-by-doing approach using chapter laboratory exercises and problems. These exercises together with the bibliography help readers deepen their understanding and widen their views of digital integrated circuits, making the book ideal for either a classroom resource or for independent study. Though there are laboratory activities, most of the analyses are theoretical and require a good understanding of calculus. ^BSumming Up: Recommended. Upper-division undergraduates through professionals. F. M. Fayemi Indiana State University

1 Introduction to Digital Integrated Circuits	p. 1
1.1 The Technological Revolution	p. 1
1.2 Electrical Properties of Digital Integrated Circuits	p. 3
1.3 Logic Families	p. 16
1.4 Computer-Aided Design and Verification	p. 17
1.5 Fabrication	p. 18
1.6 Testing and Yield	p. 30
1.7 Packaging	p. 32
1.8 Reliability	p. 33
1.9 Burn-In and Accelerated Testing	p. 36
1.10 Staying Current in the Field	p. 37
1.11 Summary	p. 37
Problems	p. 41
References	p. 41
2 Semiconductor Materials	p. 45
2.1 Introduction	p. 45
2.2 Crystal Structure	p. 45
2.3 Energy Bands	p. 47
2.4 Carrier Concentrations	p. 49
2.5 Lifetime	p. 52
2.6 Current Transport	p. 54
2.7 Carrier Continuity Equations	p. 56
2.8 Poisson's Equation	p. 57
2.9 Dielectric Relaxation Time	p. 58
2.10 Summary	p. 58
Problems	p. 60
References	p. 60
3 Diodes	p. 61
3.1 Introduction	p. 61
3.2 Zero Bias (Thermal Equilibrium)	p. 62
3.3 Forward Bias	p. 67
3.4 Reverse Bias	p. 71
3.5 Switching Transients	p. 73
3.6 Metal-Semiconductor Diode	p. 77
3.7 SPICE Models	p. 78
3.8 Integrated Circuit Diodes	p. 79
3.9 PSPICE Simulations	p. 80
3.10 Summary	p. 84
Laboratory Exercises	p. 86
Problems	p. 86
References	p. 87
4 Bipolar Junction Transistors	p. 89
4.1 Introduction	p. 89
4.2 The Bipolar Junction Transistor in Equilibrium	p. 89
4.3 DC Operation of the Bipolar Junction Transistor	p. 90
4.4 Ebers-Moll Model	p. 101
4.5 SPICE Model	p. 102
4.6 Integrated Bipolar Junction Transistors	p. 105
4.7 PSPICE Simulations	p. 106
4.8 Summary	p. 109
Laboratory Exercises	p. 111
Problems	p. 111
References	p. 113
5 Transistor-Transistor Logic	p. 115
5.1 Introduction	p. 115
5.2 Circuit Evolution	p. 115
5.3 Using Kirchhoff's Voltage Law (KVL) in TTL Circuits	p. 123
5.4 Voltage Transfer Characteristic	p. 125
5.5 Dissipation	p. 128
5.6 Fan-Out	p. 132
5.7 Propagation Delays	p. 135
5.8 Logic Design	p. 148
5.9 Schottky TTL	p. 151
5.10 PSPICE Simulations: BJT Inverter	p. 166
5.11 PSPICE Simulations: TTL	p. 168
5.12 PSPICE Simulations: LSTTL	p. 171
5.13 Summary	p. 174
Laboratory Exercises	p. 180
Problems	p. 187
References	p. 206
6 Emitter-Coupled Logic	p. 207
6.1 Introduction	p. 207
6.2 Circuit Evolution	p. 208
6.3 Using Kirchhoff's Voltage Law with ECL Circuits	p. 211
6.4 Voltage Transfer Characteristic	p. 212
6.5 Dissipation	p. 218
6.6 Propagation Delays	p. 221
6.7 Logic Design	p. 224
6.8 Temperature Effects in ECL	p. 227
6.9 ECL Circuit Families	p. 228
6.10 Active Pull-Down ECL (APD ECL)	p. 232
6.11 Low-Voltage ECL (LV-ECL)	p. 234
6.12 PSPICE Simulations	p. 236
6.13 Summary	p. 241
Laboratory Exercises	p. 245
Problems	p. 248
References	p. 253
7 Field-Effect Transistors	p. 255
7.1 Introduction	p. 255
7.2 MOS Capacitor	p. 258
7.3 MOSFET Threshold Voltage	p. 261
7.4 Long-Channel MOSFET Operation	p. 264
7.5 Short-Channel MOSFETs	p. 274
7.6 MOSFET SPICE Models	p. 277
7.7 Integrated MOSFETs	p. 279
7.8 PSPICE Simulations	p. 280
7.9 Summary	p. 282
Laboratory Exercises	p. 284
Problems	p. 284
References	p. 286
8 NMOS Logic	p. 287
8.1 Introduction	p. 287
8.2 Circuit Evolution	p. 287
8.3 Voltage Transfer Characteristic	p. 288
8.4 Dissipation	p. 296
8.5 Propagation Delays	p. 298
8.6 Fan-Out	p. 301
8.7 Logic Design	p. 303
8.8 PSPICE Simulations	p. 307
8.9 Summary	p. 310
Laboratory Exercises	p. 312
Problems	p. 315
Reference	p. 319
9 CMOS Logic	p. 321
9.1 Introduction	p. 321
9.2 Voltage Transfer Characteristic	p. 322
9.3 Short-Circuit Current in CMOS	p. 326
9.4 Propagation Delays	p. 329
9.5 Dissipation	p. 332
9.6 Fan-Out	p. 338
9.7 Logic Design	p. 339
9.8 4000 Series CMOS	p. 342
9.9 74HCxx Series CMOS	p. 345
9.10 Buffered CMOS	p. 349
9.11 Pseudo NMOS	p. 354
9.12 Dynamic CMOS	p. 356
9.13 Domino Logic	p. 361
9.14 Latch-Up in CMOS	p. 362
9.15 Static Discharge in CMOS	p. 364
9.16 Scaling of CMOS	p. 365
9.17 PSPICE Simulations	p. 367
9.18 Summary	p. 375
Laboratory Exercises	p. 378
Problems	p. 383
References	p. 388
10 Low-Power CMOS Logic	p. 391
10.1 Introduction	p. 391
10.2 Low-Voltage CMOS	p. 392
10.3 Multiple Voltage CMOS	p. 394
10.4 Dynamic Voltage Scaling	p. 396
10.5 Active Body Biasing	p. 397
10.6 Multiple Threshold CMOS	p. 400
10.7 Adiabatic Logic	p. 403
10.8 Silicon-on-Insulator (SOI)	p. 407
10.9 Summary	p. 415
Problems	p. 418
References	p. 419
11 BiCMOS Logic	p. 423
11.1 Introduction	p. 423
11.2 Voltage Transfer Characteristic	p. 423
11.3 Propagation Delays	p. 425
11.4 Rail-to-Rail BiCMOS	p. 429
11.5 Logic Design	p. 431
11.6 PSPICE Simulations	p. 432
11.7 Summary	p. 436
Laboratory Exercises	p. 439
Problems	p. 442
References	p. 447
12 GaAs Direct-Coupled FET Logic	p. 449
12.1 Introduction	p. 449
12.2 Gallium Arsenide vs. Silicon	p. 449
12.3 Gallium Arsenide MESFET	p. 451
12.4 Metal-Semiconductor Junction	p. 451
12.5 MESFET Pinch-Off Voltage	p. 452
12.6 Long-Channel MESFET Operation	p. 454
12.7 Short-Channel MESFETs	p. 457
12.8 The Curtice Model for the MESFET	p. 459
12.9 MESFET SPICE Model	p. 462
12.10 Integrated MESFETs	p. 463
12.11 Direct-Coupled FET Logic (DCFL)	p. 464
12.12 PSPICE Simulations	p. 470
12.13 Summary	p. 473
Problems	p. 476
References	p. 479
13 Interfacing between Digital Logic Circuits	p. 481
13.1 Introduction	p. 481
13.2 Level-Shifting Circuits	p. 481
13.3 Wired Logic	p. 488
13.4 Transmission Gates	p. 490
13.5 Tri-State Logic	p. 490
13.6 PSPICE Simulations	p. 494
13.7 Summary	p. 499
Laboratory Exercises	p. 502
Problems	p. 505
References	p. 507
14 Interconnect	p. 509
14.1 Introduction	p. 509
14.2 Capacitance of Interconnect	p. 510
14.3 Resistance of Interconnect	p. 513
14.4 Inductance of Interconnect	p. 517
14.5 Lumped Capacitance Model	p. 518
14.6 Distributed Models	p. 518
14.7 Transmission Line Model	p. 521
14.8 Special Problems in Interconnect Design	p. 525
14.9 PSPICE Simulations	p. 530
14.10 Summary	p. 536
Problems	p. 538
References	p. 540
15 Bistable Circuits	p. 543
15.1 Introduction	p. 543
15.2 RS Latch	p. 545
15.3 RS Flip-Flop	p. 547
15.4 JK Flip-Flop	p. 547
15.5 Other Flip-Flops	p. 550
15.6 Schmitt Triggers	p. 551
15.7 PSPICE Simulations	p. 561
15.8 Summary	p. 566
Laboratory Exercises	p. 568
Problems	p. 570
References	p. 576
16 Digital Memories	p. 577
16.1 Introduction	p. 577
16.2 Static Random Access Memory (SRAM)	p. 579
16.3 Dynamic Random Access Memory (DRAM)	p. 583
16.4 Read-Only Memory (ROM)	p. 585
16.5 Programmable Read-Only Memory (PROM)	p. 589
16.6 Erasable Programmable Read-Only Memory (EPROM)	p. 591
16.7 Electrically Erasable Programmable Read-Only Memory (EEPROM)	p. 593
16.8 Flash Memory	p. 595
16.9 Access Times in Digital Memories	p. 596
16.10 Emerging Memory Concepts	p. 597
16.11 Summary	p. 601
Problems	p. 603
References	p. 603
17 Design and Layout	p. 607
17.1 Introduction	p. 607
17.2 Photolithography and Masks	p. 607
17.3 Layout and Design Rules	p. 610
17.4 Physical Design of CMOS Circuits	p. 618
17.5 VLSI Design Principles	p. 619
17.6 Summary	p. 625
Problems	p. 630
References	p. 632
18 Integrated Circuit Packages	p. 635
18.1 Introduction	p. 635
18.2 Package Types	p. 635
18.3 General Considerations	p. 643
18.4 Packaging Processes and Materials	p. 651
18.5 Summary	p. 656
Problems	p. 659
References	p. 659
Appendix A Properties of Si and GaAs at 300 K	p. 663
Appendix B Design Rules, Constants, Symbols, and Definitions	p. 665
B.1 Design Rules	p. 665
B.2 Constants	p. 665
B.3 Symbols	p. 665
B.4 Definitions	p. 670
Index	p. 673

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