Basics of CMOS cell design

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Design and Simulate Any Type of CMOS Circuit!

Electronic circuit designers and electronic engineering students can turn to Basics of CMOS Cell Design for a practice-based introduction to the design and simulation of every major type of CMOS (complementary metal oxide semiconductor) integrated circuit.

You will find step-by-step explanations of everything they need for designing and simulating CMOS integrated circuits in deep-submicron technology, including MOS devices...inverters...interconnects...basic gates ...arithmetics...sequential cell design...and analog basic cells.

The book also presents design rules, Microwind program operation and commands, design logic editor operation and commands, and quick-reference sheets. Filled with 100 skills-building illustrations, Basics of CMOS Cell Design features:

Expert guidance on MOS device modeling Complete details on micron and deep-submicron technologies Clear, concise information on basic logic gates Full coverage of analog cells A wealth of circuit simulation tools

Inside This Landmark CMOS Circuit Design Guide--

* MOS Devices and Technology * MOS Modeling * The Inverter * Interconnects * Basic Gates * Arithmetics * Sequential Cell Design * Analog Cells * Appendices: Design Rules; Microwind Program Operation and Commands; Design Logic Editor Operation and Commands; Quick- Reference Sheets

Author Notes

Dr. Etienne Sicard is professor of electronic engineering at the INSA Electronic Engineering School of Toulouse, France
Dr. Sonia Delmas Bendhia is a senior lecturer in the Department of Electrical and Computer Engineering at the INSA Electronic Engineering School of Toulouse, France

Preface	p. vii
Acknowledgments	p. ix
Abbreviations and Symbols	p. xv
1 Introduction	p. 1
1.1 General Trends	p. 1
1.2 The Device Scale Down	p. 5
1.3 Frequency Improvements	p. 5
1.4 Layers	p. 6
1.5 Density	p. 8
1.6 Design Trends	p. 10
1.7 Market	p. 11
1.8 Conclusion	p. 11
References	p. 11
Exercises	p. 12
2 The MOS Devices and Technology	p. 13
2.1 Properties of Silicon	p. 13
2.2 N-type and P-type Silicon	p. 16
2.3 Silicon Dioxide	p. 18
2.4 Metal Materials	p. 19
2.5 The MOS Switch	p. 20
2.6 The MOS Aspect	p. 23
2.7 MOS Layout	p. 25
2.8 Dynamic MOS Behaviour	p. 32
2.9 The Perfect Switch	p. 38
2.10 Layout Considerations	p. 41
2.11 CMOS Process	p. 44
2.12 Conclusion	p. 48
References	p. 48
Exercises	p. 48
3 The MOS Modelling	p. 51
3.1 Introduction to Modelling	p. 51
3.2 MOS Model 1	p. 53
3.3 MOS Model 3	p. 57
3.4 The BSIM4 MOS Model	p. 66
3.5 Specific MOS Devices	p. 80
3.6 Process Variations	p. 87
3.7 Concluding Remarks	p. 90
References	p. 91
Exercises	p. 91
4 The Inverter	p. 93
4.1 Logic Symbol	p. 93
4.2 CMOS Inverter	p. 94
4.3 Inverter Layout	p. 95
4.4 Inverter Simulation	p. 104
4.5 Power Consumption	p. 111
4.6 Static Characteristics	p. 114
4.7 Random Simulation	p. 118
4.8 The Inverter as a Library Cell	p. 120
4.9 3-State Inverter	p. 122
4.10 All nMOS Inverters	p. 125
4.11 Ring Oscillator	p. 127
4.12 Latch-up Effect	p. 133
4.13 Conclusion	p. 134
References	p. 134
Exercises	p. 135
5 Interconnects	p. 137
5.1 Introduction	p. 137
5.2 Metal Layers	p. 137
5.3 Contact and Vias	p. 139
5.4 Design Rules	p. 142
5.5 Capacitance Associated with Interconnects	p. 146
5.6 Resistance Associated with Interconnects	p. 153
5.7 Signal Transport	p. 157
5.8 Improved Signal Transport	p. 164
5.9 Repeaters for Improved Signal Transport	p. 167
5.10 Crosstalk Effects in Interconnects	p. 169
5.11 Antenna Effect	p. 173
5.12 Inductance	p. 176
5.13 Conclusion	p. 179
References	p. 179
Exercises	p. 180
6 Basic Gates	p. 182
6.1 Introduction	p. 182
6.2 Combinational Logic	p. 182
6.3 CMOS Logic Gate Concept	p. 184
6.4 The NAND Gate	p. 185
6.5 The AND Gate	p. 202
6.6 The NOR Gate	p. 204
6.7 The OR Gate	p. 207
6.8 The XOR Gate	p. 208
6.9 Complex Gates	p. 214
6.10 Multiplexor	p. 218
6.11 Shifters	p. 227
6.12 Description of Basic Gates in Verilog	p. 229
6.13 Conclusion	p. 231
References	p. 231
Exercises	p. 231
7 Arithmetics	p. 233
7.1 Data Formats	p. 233
7.2 The Adder Circuit	p. 236
7.3 Adder Cell Design	p. 238
7.4 Ripple-carry Adder	p. 247
7.5 Signed Adder	p. 253
7.6 Fast Adder Circuits	p. 254
7.7 Substractor Circuit	p. 258
7.8 Comparator Circuit	p. 260
7.9 Student Project: A Decimal Adder	p. 262
7.10 Multiplier	p. 267
7.11 Conclusion	p. 272
References	p. 272
Exercises	p. 273
8 Sequential Cell Design	p. 274
8.1 The Elementary Latch	p. 274
8.2 RS Latch	p. 275
8.3 D Latch	p. 282
8.4 Edge-trigged D Register	p. 288
8.5 Clock Divider	p. 295
8.6 Synchronous Counters	p. 299
8.7 Shift Registers	p. 301
8.8 A 24-hour Clock	p. 303
8.9 Conclusion	p. 307
References	p. 307
Exercises	p. 307
9 Analog Cells	p. 309
9.1 Resistor	p. 309
9.2 Capacitor	p. 314
9.3 The MOS Device for Analog Design	p. 321
9.4 Diode-connected MOS	p. 324
9.5 Voltage Reference	p. 326
9.6 Current Mirror	p. 331
9.7 The MOS Transconductance	p. 335
9.8 Single Stage Amplifier	p. 336
9.9 Simple Differential Amplifier	p. 345
9.10 Wide Range Amplifier	p. 354
9.11 On-chip Voltage Regulator	p. 357
9.12 Noise	p. 359
9.13 Conclusion	p. 361
References	p. 361
Exercises	p. 361
10 Conclusion	p. 363
Appendices
A Design Rules	p. 364
A.1 Lambda Units	p. 364
A.2 Layout Design Rules	p. 365
A.3 Pads	p. 368
A.4 Electrical Extraction Principles	p. 368
A.5 Node Capacitance Extraction	p. 369
A.6 Resistance Extraction	p. 372
A.7 Simulation Parameters	p. 373
A.8 Technology Files for Dsch	p. 376
B Microwind Program Operation and Commands	p. 378
B.1 Getting Started	p. 378
B.2 List of Commands in Microwind	p. 379
C Dsch Logic Editor Operation and Commands	p. 403
C.1 Getting Started	p. 403
C.2 Commands	p. 403
D Quick Reference Sheet	p. 413
D.1 Microwind Menus	p. 413
D.2 Microwind Simulation Menu	p. 416
D.3 Dsch Menus	p. 417
D.4 List of Files	p. 419
D.5 List of Measurement Files	p. 419
Glossary	p. 422
Index	p. 424
Software Download Information	p. 428
Authors' Profiles	p. 429

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Author Notes

Table of Contents