Introduction to VLSI circuits and systems

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Title:

Personal Author:

Uyemura, John P. (John Paul), 1952-

Publication Information:

Hoboken, N.J. : John Wiley, 2002

Physical Description:

1v + 1 CD-ROM (CP 2790)

ISBN:

9780471127048

Subject Term:

Integrated circuits -- Very large scale integration

Digital electronics

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010052132	TK7874 U934 2002	Open Access Book	Book	Searching... Unknown

Presents modern CMOS logic circuits, fabrication, and layout in a cohesive manner that links the material together with the system-level considerations.
* Chapter on Verilog HDL allows for rapid start-up.
* Illustrates the top-down design procedure used in modern VLSI chip design with an emphasis on variations in the HDL, logic, circuits and layout.

Preface	p. iv
Table of Contents	p. ix
Chapter 1 An Overview of VLSI	p. 1
1.1 Complexity and Design	p. 1
1.2 Basic Concepts	p. 7
1.3 Plan of the Book	p. 11
1.4 General References	p. 11
Part 1 Silicon Logic
Chapter 2 Logic Design with MOSFETs	p. 15
2.1 Ideal Switches and Boolean Operations	p. 15
2.2 MOSFETs as Switches	p. 20
2.3 Basic Logic Gates in CMOS	p. 28
2.4 Complex Logic Gates in CMOS	p. 40
2.5 Transmission Gate Circuits	p. 55
2.6 Clocking and Dataflow Control	p. 60
2.7 Further Reading	p. 63
2.8 Problems	p. 64
Chapter 3 Physical Structure of CMOS Integrated Circuits	p. 67
3.1 Integrated Circuit Layers	p. 67
3.2 MOSFETs	p. 75
3.3 CMOS Layers	p. 93
3.4 Designing FET Arrays	p. 96
3.5 References for Further Reading	p. 110
3.6 Problems	p. 110
Chapter 4 Fabrication of CMOS Integrated Circuits	p. 115
4.1 Overview of Silicon Processing	p. 115
4.2 Material Growth and Deposition	p. 119
4.3 Lithography	p. 126
4.4 The CMOS Process Flow	p. 132
4.5 Design Rules	p. 140
4.6 Further Reading	p. 146
Chapter 5 Elements of Physical Design	p. 147
5.1 Basic Concepts	p. 147
5.2 Layout of Basic Structures	p. 150
5.3 Cell Concepts	p. 167
5.4 FET Sizing and the Unit Transistor	p. 173
5.5 Physical Design of Logic Gates	p. 180
5.6 Design Hierarchies	p. 184
5.7 References for Further Reading	p. 187
Part 2 The Logic-Electronics Interface
Chapter 6 Electrical Characteristics of MOSFETs	p. 191
6.1 MOS Physics	p. 191
6.2 nFET Current-Voltage Equations	p. 198
6.3 The FET RC Model	p. 212
6.4 pFET Characteristics	p. 223
6.5 Modeling of Small MOSFETs	p. 229
6.6 References for Further Reading	p. 235
6.7 Problems	p. 235
Chapter 7 Electronic Analysis of CMOS Logic Gates	p. 237
7.1 DC Characteristics of the CMOS Inverter	p. 237
7.2 Inverter Switching Characteristics	p. 244
7.3 Power Dissipation	p. 257
7.4 DC Characteristics: NAND and NOR Gates	p. 260
7.5 NAND and NOR Transient Response	p. 266
7.6 Analysis of Complex Logic Gates	p. 272
7.7 Gate Design for Transient Performance	p. 276
7.8 Transmission Gates and Pass Transistors	p. 281
7.9 Comments on SPICE Simulations	p. 285
7.10 References for Further Study	p. 288
7.11 Problems	p. 288
Chapter 8 Designing High-Speed CMOS Logic Networks	p. 293
8.1 Gate Delays	p. 293
8.2 Driving Large Capacitive Loads	p. 303
8.3 Logical Effort	p. 313
8.4 BiCMOS Drivers	p. 327
8.5 Books for Further Reading	p. 335
8.6 Problems	p. 336
Chapter 9 Advanced Techniques in CMOS Logic Circuits	p. 339
9.1 Mirror Circuits	p. 339
9.2 Pseudo-nMOS	p. 342
9.3 Tri-State Circuits	p. 344
9.4 Clocked CMOS	p. 346
9.5 Dynamic CMOS Logic Circuits	p. 353
9.6 Dual-Rail Logic Networks	p. 360
9.7 Additional Reading	p. 366
9.8 Problems	p. 366
Part 3 The Design of VLSI Systems
Chapter 10 System Specifications Using Verilog HDL	p. 371
10.1 Basic Concepts	p. 371
10.2 Structural Gate-Level Modeling	p. 373
10.3 Switch-Level Modeling	p. 383
10.4 Design Hierarchies	p. 388
10.5 Behavioral and RTL Modeling	p. 392
10.6 References	p. 399
10.7 Problems	p. 400
Chapter 11 General VLSI System Components	p. 403
11.1 Multiplexors	p. 403
11.2 Binary Decoders	p. 411
11.3 Equality Detectors and Comparators	p. 413
11.4 Priority Encoder	p. 417
11.5 Shift and Rotation Operations	p. 420
11.6 Latches	p. 424
11.7 D Flip-Flop	p. 431
11.8 Registers	p. 436
11.9 The Role of Synthesis	p. 439
11.10 References for Further Study	p. 440
11.11 Problems	p. 441
Chapter 12 Arithmetic Circuits in CMOS VLSI	p. 443
12.1 Bit Adder Circuits	p. 443
12.2 Ripple-Carry Adders	p. 451
12.3 Carry Look-Ahead Adders	p. 454
12.4 Other High-Speed Adders	p. 467
12.5 Multipliers	p. 471
12.6 Summary	p. 481
12.7 References	p. 481
12.8 Problems	p. 481
Chapter 13 Memories and Programmable Logic	p. 483
13.1 The Static RAM	p. 483
13.2 SRAM Arrays	p. 488
13.3 Dynamic RAMs	p. 498
13.4 ROM Arrays	p. 506
13.5 Logic Arrays	p. 513
13.6 References	p. 519
13.7 Problems	p. 519
Chapter 14 System-Level Physical Design	p. 523
14.1 Large-Scale Physical Design	p. 523
14.2 Interconnect Delay Modeling	p. 525
14.3 Crosstalk	p. 536
14.4 Interconnect Scaling	p. 542
14.5 Floorplanning and Routing	p. 544
14.6 Input and Output Circuits	p. 549
14.7 Power Distribution and Consumption	p. 558
14.8 Low-Power Design Considerations	p. 565
14.9 References for Further Study	p. 567
14.10 Problems	p. 568
Chapter 15 VLSI Clocking and System Design	p. 571
15.1 Clocked Flip-flops	p. 571
15.2 CMOS Clocking Styles	p. 575
15.3 Pipelined Systems	p. 589
15.4 Clock Generation and Distribution	p. 594
15.5 System Design Considerations	p. 606
15.6 References for Advanced Reading	p. 611
Chapter 16 Reliability and Testing of VLSI Circuits	p. 613
16.1 General Concepts	p. 613
16.2 CMOS Testing	p. 620
16.3 Test Generation Methods	p. 627
16.4 Summary	p. 636
16.5 References	p. 636
Index	p. 637

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