CMOS integrated analog-to-digital and digital-to-analog converters

CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes in depth converter specifications like Effective Number of Bits (ENOB), Spurious Free Dynamic Range (SFDR), Integral Non-Linearity (INL), Differential Non-Linearity (DNL) and sampling clock jitter requirements. Relations between these specifications and practical issues like matching of components and offset parameters of differential pairs are derived.

CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes the requirements of input and signal reconstruction filtering in case a converter is applied into a signal processing system.

CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes design details of high-speed A/D and D/A converters, high-resolution A/D and D/A converters, sample-and-hold amplifiers, voltage and current references, noise-shaping converters and sigma-delta converters, technology parameters and matching performance, comparators and limitations of comparators and finally testing of converters.

List of figures	p. xiii
List of tables	p. xxvii
List of symbols	p. xxix
Preface	p. xxxv
1 The converter as a black box	p. 1
1.1 Introduction	p. 1
1.2 Basic D/A and A/D converter function	p. 2
1.3 Classification of signals	p. 5
1.4 Quantization errors	p. 7
1.5 Oversampling of converters	p. 10
1.6 Quantization error spectra	p. 12
1.7 Amplitude dependence of quantization components	p. 16
1.8 Multiple signal distortion	p. 17
1.9 Accurate dynamic range calculation	p. 19
1.10 Sampling time uncertainty	p. 21
1.11 Sampling clock time uncertainty	p. 25
1.12 Conversion systems	p. 27
1.13 Nyquist filtering in A/D converter systems	p. 31
1.14 Combined analog and digital filter	p. 32
1.15 Output filtering in D/A converter systems	p. 34
1.16 Dynamic range and alias filter order	p. 41
1.17 Analog filter designs	p. 42
1.18 Minimum required stop band attenuation	p. 45
1.19 Conclusion	p. 48
2 Specifications of converters	p. 51
2.1 Introduction	p. 51
2.2 Digital data coding	p. 52
2.3 Digital coding schemes	p. 53
2.4 Ideal and Non-ideal converters	p. 55
2.5 DC specifications	p. 57
2.6 Dynamic specifications	p. 65
2.7 Figure of Merit	p. 103
2.8 Conclusion	p. 104
3 High-speed A/D converters	p. 107
3.1 Introduction	p. 107
3.2 Design problems in high-speed converters	p. 110
3.3 Internal converter coding schemes	p. 112
3.4 Full-flash converters	p. 115
3.5 Interpolation	p. 118
3.6 Averaging	p. 124
3.7 6-bit converter implementation	p. 130
3.8 Discrete time flash converter	p. 134
3.9 Gray code full flash converters	p. 138
3.10 Circular code flash converters	p. 142
3.11 Two-step flash converters	p. 144
3.12 Sub ranging converter architecture	p. 148
3.13 Pipeline converter architecture	p. 160
3.14 Folding converter system	p. 169
3.15 Time interleaved high-speed converters	p. 195
3.16 Minimum supply voltage calculation	p. 198
3.17 Reference ladder signal feedthrough	p. 199
3.18 Bubble correction	p. 200
3.19 Delay over interconnect lines	p. 201
3.20 Conclusion	p. 203
4 High-speed D/A converters	p. 205
4.1 Introduction	p. 205
4.2 High-speed D/A converter architectures	p. 205
4.3 Voltage weighting based architecture	p. 208
4.4 High-speed segmented converter architecture	p. 214
4.5 Conclusion	p. 234
5 High-resolution A/D converters	p. 237
5.1 Introduction	p. 237
5.2 Single slope A/D converter system	p. 238
5.3 Dual-slope A/D converter system	p. 240
5.4 Dual-ramp single-slope A/D converter system	p. 241
5.5 Successive approximation converter system	p. 244
5.6 Algorithmic A/D converter	p. 254
5.7 Cyclic Redundant Signed Digit A/D converter	p. 256
5.8 Self-calibrating capacitor A/D converter	p. 260
5.9 Conclusion	p. 262
6 High-resolution D/A converters	p. 263
6.1 Introduction	p. 263
6.2 Pulse-width modulation D/A converters	p. 264
6.3 Integrating D/A converters	p. 266
6.4 Current weighting using ladder networks	p. 270
6.5 Monotonic by design network systems	p. 280
6.6 Self calibrating D/A converter system	p. 287
6.7 Dynamic Element Matching	p. 289
6.8 Current calibration principle	p. 302
6.9 Conclusion	p. 311
7 Sample-and-hold amplifiers	p. 313
7.1 Introduction	p. 313
7.2 Basic sample-and-hold configuration	p. 314
7.3 Generalized non-inverting configurations	p. 335
7.4 Inverting sample-and-hold circuit	p. 345
7.5 Operational range of simple sample-and-hold amplifiers	p. 346
7.6 Conclusion	p. 347
8 Noise-shaping D/A conversion	p. 349
8.1 Introduction	p. 349
8.2 Digital oversampling filtering	p. 350
8.3 Noise-shaping	p. 353
8.4 Multi-bit largely oversampled noise-shaper	p. 370
8.5 Stability analysis of noise-shapers	p. 371
8.6 Practical noise-shaping D/A converters	p. 391
8.7 Multi-bit noise-shaping D/A converter	p. 403
8.8 Conclusion	p. 415
9 Sigma-delta A/D conversion	p. 417
9.1 Introduction	p. 417
9.2 General form of Sigma-delta A/D converters	p. 418
9.3 General filter architectures	p. 423
9.4 Discussion of basic converter architectures	p. 432
9.5 Multi-stage sigma-delta converter (MASH)	p. 437
9.6 Quantizer overload avoidance	p. 438
9.7 Converter input circuitry	p. 441
9.8 Practical 16-bit cascaded converter	p. 445
9.9 Feed-forward A/D converter system	p. 445
9.10 Nth-order sigma-delta architecture	p. 451
9.11 Bandpass sigma-delta converters	p. 454
9.12 Low-pass to band-pass transformation	p. 454
9.13 Continuous time band-pass converter	p. 458
9.14 Limited gain in loop filter	p. 463
9.15 Idle pattern	p. 463
9.16 Sigma-delta digital voltmeter	p. 469
9.17 Conclusion	p. 475
10 Voltage and current references	p. 477
10.1 Introduction	p. 477
10.2 Gate-source voltage used as a reference	p. 477
10.3 Basic band-gap reference voltage source	p. 479
10.4 Conclusion	p. 484
11 Limitations of comparators	p. 485
11.1 Signal delay in limiting amplifiers	p. 485
11.2 Definition of the delay problem	p. 486
11.3 Delay calculation model	p. 487
11.4 Variable delay calculation	p. 489
11.5 Distortion calculation	p. 495
11.6 Failure analysis of comparators	p. 499
11.7 Current mode comparator circuit	p. 504
11.8 Differential auto-zero comparator	p. 506
11.9 Complementary comparator with latch	p. 508
11.10 Low kick back comparator implementation	p. 509
11.11 Input frequency decision moment variation	p. 510
11.12 Conclusion	p. 510
12 Technology and device matching	p. 513
12.1 Introduction	p. 513
12.2 Technology road map	p. 513
12.3 MOS matching models	p. 514
12.4 Capacitor matching	p. 520
12.5 Resistor matching	p. 521
12.6 Conclusion	p. 522
13 Testing of D/A and A/D converters	p. 523
13.1 Introduction	p. 523
13.2 DC testing of D/A converters	p. 523
13.3 Dynamic testing of D/A converters	p. 526
13.4 DC testing of A/D converters	p. 531
13.5 Dynamic testing of A/D converters	p. 532
13.6 Bit Error Rate	p. 535
13.7 Testing very high-speed A/D converters	p. 536
13.8 Beat frequency test configuration	p. 539
13.9 Code density DNL and INL measurement	p. 540
13.10 Testing of sample-and-hold amplifiers	p. 544
13.11 Cascading sample-and-hold amplifiers	p. 548
13.12 Conclusion	p. 549
Bibliography	p. 551
Index	p. 567

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