Silicon wafer bonding technology : for VLSI and MEMS applications

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Title:

Publication Information:

London : INSPEC, 2002

ISBN:

9780852960394

Subject Term:

Silicon-on-insulator technology

Integrated circuits -- Very large scale integration

Microelectromechanical systems

Added Author:

Iyer, Subramanian S.

Auberton-Herve, Andre J.

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Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010019235	TK7871.85 S55 2002	Open Access Book	Book	Searching... Unknown

By bonding a thin wafer of active silicon to a thicker wafer via a layer of insulating oxide to form an SOI structure it is possible to substantially improve the performance and integration of microelectronic circuits produced by very large scale integration (VLSI). For example, the recently announced IBM Power 4 'server-ona- chip' integrates two microprocessors, a high bandwidth system switch, a large memory cache and input/output functions. SOI wafer bonding is also an enabling technology in the rapidly growing field of microelectromechanical systems (MEMS).

Engineers who are developing volume production systems employing wafer bonding are in need of guidance from experts in the industry who have been pioneering the field and the book is designed for this purpose. It briefs the process development engineer on the latest emerrging technology, giving the reader the benefit of RandD by companies at the forefront of SOI, and also describes the basic principles. Applications in CMOS, photonics, optoelectronics and MEMS are discussed , there is a glossary of terms used in the field and a table comparing the various bonding methods. Although the main focus is on SOI there is also an appendix which describes a practical silicon-to-silicon bonding process and gives useful information relevant to wafer bonding in general.

s in CMOS, photonics, optoelectronics and MEMS are discussed , there is a glossary of terms used in the field and a table comparing the various bonding methods. Although the main focus is on SOI there is also an appendix which describes a practical silicon-to-silicon bonding process and gives useful information relevant to wafer bonding in general.s in CMOS, photonics, optoelectronics and MEMS are discussed , there is a glossary of terms used in the field and a table comparing the various bonding methods. Although the main focus is on SOI there is also an appendix which describes a practical silicon-to-silicon bonding process and gives useful information relevant to wafer bonding in general.s in CMOS, photonics, optoelectronics and MEMS are discussed , there is a glossary of terms used in the field and a table comparing the various bonding methods. Although the main focus is on SOI there is also an appendix which describes a practical silicon-to-silicon bonding process and gives useful information relevant to wafer bonding in general.

S.S. IyerQ.-Y. TongK. MitaniB. Aspar and A.J. Auberton-HerveT. YoneharaG. Pfeiffer and S.S. IyerE.C. Jones and S.W. BedellI.K. Bansal and J.P. Goodrich

Dedication	p. ix
Editors	p. xi
Authors	p. xiii
Abbreviations	p. xvii
Introduction and overview	p. xix
1 Principles of wafer bonding	p. 1
1.1 Introduction	p. 1
1.2 Wafer Bonding Basics	p. 3
1.2.1 Surface smoothness	p. 3
1.2.2 Surface flatness	p. 5
1.2.3 Surface cleanliness	p. 7
1.2.4 Standard wafer bonding and layer transfer procedures	p. 7
1.3 Generic Nature of Wafer Bonding	p. 13
1.4 Low Temperature Wafer Bonding	p. 13
1.4.1 Introduction	p. 13
1.4.2 Room temperature covalent bonding	p. 14
1.4.3 Low temperature epitaxial wafer bonding	p. 16
1.5 Summary	p. 18
2 Bond, grind-back and polish SOI	p. 21
2.1 Introduction	p. 21
2.2 Processing	p. 21
2.2.1 Fabrication process flow	p. 21
2.2.2 Initial bonding	p. 22
2.2.3 Bonding anneal	p. 24
2.2.4 Thinning by grinding and polishing	p. 25
2.2.5 Thinning by PACE	p. 29
2.2.6 Wafer size availability	p. 30
2.3 Physical and Electrical Properties	p. 30
2.3.1 Warpage and stress	p. 30
2.3.2 Crystal defects	p. 31
2.3.3 Fixed charges in BOX	p. 33
2.4 Summary	p. 34
3 Smart Cut: the technology used for high volume SOI wafer production	p. 35
3.1 Introduction	p. 35
3.2 Processing	p. 35
3.3 Physical Mechanisms	p. 36
3.3.1 Effect of hydrogen implantation in silicon	p. 36
3.3.2 Splitting kinetics	p. 41
3.3.3 Cleaning and bonding	p. 43
3.4 Applications	p. 44
3.4.1 Introduction	p. 44
3.4.2 Silicon on insulator wafers	p. 44
3.4.3 Transfer of thin semiconductor films on new bonded layers	p. 46
3.4.4 Transfer of materials other than silicon	p. 48
3.5 Summary	p. 49
4 ELTRAN (SOI-Epi wafer) technology	p. 53
4.1 Introduction	p. 53
4.2 Special Features of ELTRAN	p. 53
4.2.1 SOI-Epi wafer	p. 53
4.2.2 Surface smoothing techniques	p. 54
4.2.3 Film thickness control	p. 56
4.2.4 Cloning (wafer recycling)	p. 56
4.3 Processing	p. 56
4.3.1 Introduction	p. 56
4.3.2 Anodization	p. 57
4.3.3 Epitaxial growth	p. 58
4.3.4 Bonding and splitting	p. 59
4.3.5 Etching	p. 60
4.3.6 Hydrogen annealing	p. 62
4.4 Applicability and Comparisons	p. 63
4.4.1 SOI/BOX thickness requirement for various SOI device applications	p. 63
4.4.2 Ultra thin SOI	p. 64
4.4.3 Comparisons	p. 67
4.5 Cost Reduction and Scalability	p. 70
4.5.1 Introduction	p. 70
4.5.2 Recycling of seed wafer	p. 70
4.5.3 Double porous Si layers	p. 72
4.5.4 Splitting with a water jet	p. 74
4.5.5 300 mm wafer SOI	p. 77
4.6 Summary	p. 78
5 Wafer characterization	p. 83
5.1 Introduction	p. 83
5.2 Characterization Techniques	p. 84
5.2.1 Bonding strength/layer integrity	p. 84
5.2.2 Layer thickness measurements	p. 85
5.2.3 Surface characterization	p. 86
5.2.4 Contamination/doping	p. 87
5.2.5 Defect decoration	p. 88
5.2.6 Pseudo MOSFET	p. 88
5.2.7 BOX measurements	p. 90
5.3 Summary	p. 91
6 Advanced applications of wafer bonding	p. 93
6.1 Introduction	p. 93
6.2 Advanced Microelectronics	p. 93
6.2.1 High performance partially depleted and fully depleted CMOS	p. 93
6.2.2 Double gate CMOS	p. 95
6.2.3 3D device integration	p. 98
6.3 Photonics and Optoelectronics	p. 102
6.3.1 Introduction	p. 102
6.3.2 Light sources	p. 102
6.3.3 Light detectors	p. 104
6.3.4 Waveguides and couplers	p. 105
6.3.5 Switches, modulators and other structures	p. 107
6.4 Compliant Substrates	p. 108
6.4.1 Introduction	p. 108
6.4.2 Thin SOI and glass-bonded compliant substrates	p. 109
6.4.3 Twist bonded compliant substrates	p. 111
6.5 Microelectromechanical Systems (MEMS)	p. 113
6.5.1 Introduction	p. 113
6.5.2 MEMS background	p. 114
6.5.3 Wafer bonding as an enabling technology for MEMS	p. 115
6.6 Monolithic Integration	p. 117
6.7 Summary	p. 118
Appendix 1 A manufacturing process for silicon-on-silicon wafer bonding	p. 123
Summary	p. 123
A1.1 Introduction	p. 123
A1.2 Direct Wafer Bonding	p. 123
A1.2.1 Surface preparation	p. 124
A1.2.2 Contacting	p. 124
A1.2.3 Thermal annealing	p. 125
A1.3 Physical Parameters of Incoming Silicon Substrates	p. 125
A1.4 Pre-join Surface Preparation	p. 126
A1.5 Ambient Temperature Bonding	p. 127
A1.6 Thermal Annealing Process	p. 128
A1.7 Analysis of Voids Within the Thermally Annealed Interface	p. 128
A1.8 Grinding of Device Layer to Semi-Finished Thickness	p. 129
A1.9 Measurement of Carrier Concentration Across the Interface Layer	p. 129
A1.10 Data and Results	p. 129
A1.10.1 Non-megasonic 'concentrated' RCA clean plus single-side-scrub (SSS)	p. 130
A1.10.2 Megasonic 'very dilute' RCA clean plus Marangoni drying	p. 131
A1.10.3 SRP analysis of bonded interface layer	p. 133
A1.11 Semiconductor Applications	p. 133
A1.12 Conclusions	p. 133
Appendix 2 Glossary	p. 135
Appendix 3 Comparison of bonded wafer technologies	p. 141
Appendix 4 Further reading and websites	p. 143
Subject index	p. 145

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