Compilers and operating systems for low power

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Title:

Publication Information:

Boston, MA : Kluwer Academic Publishers, 2003

ISBN:

9781402075735

Subject Term:

Operating systems (Computers)

Compilers (Computer programs)

Added Author:

Benini, Luca, 1967-

Kandemir, Mahmut

Ramanujam, J.

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Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ KL	30000010080260	QA76.76.O63 C654 2003	Open Access Book	Book	Searching... Unknown

Compilers and Operating Systems for Low Power focuses on both application-level compiler directed energy optimization and low-power operating systems. Chapters have been written exclusively for this volume by several of the leading researchers and application developers active in the field. The first six chapters focus on low energy operating systems, or more in general, energy-aware middleware services. The next five chapters are centered on compilation and code optimization. Finally, the last chapter takes a more general viewpoint on mobile computing. The material demonstrates the state-of-the-art work and proves that to obtain the best energy/performance characteristics, compilers, system software, and architecture must work together. The relationship between energy-aware middleware and wireless microsensors, mobile computing and other wireless applications are covered.

This work will be of interest to researchers in the areas of low-power computing, embedded systems, compiler optimizations, and operating systems.

Suet-Fei Li and Roy Sutton and Jan RabaeyM. Angels Moncusi and Alex Arenas and Jesus LabartaNevine AbouGhazaleh and Daniel Mosse and Bruce Childers and Rami MelhemAndrea Acquaviva and Luca Benini and Bruno RiccoEduardo Pinheiro and Ricardo Bianchini and Enrique V. Carrera and Taliver HeathJerry Hom and Ulrich KremerGreg Stitt and Frank VahidToshinori Sato and Itsujiro AritaWeiping Liao and Lei HeArnout Vandecappelle and Bruno Bougard and K.C. Shashidhar and Francky CatthoorPaolo D'Alberto and Alexandru Nicolau and Alexander Veidenbaum and Rajesh GuptaMichael Franz

List of Figures	p. xi
List of Tables	p. xv
Contributing Authors	p. xvii
Preface	p. xix
1 Low Power Operating System for Heterogeneous Wireless Communication System	p. 1
1 Introduction	p. 2
2 Event-driven versus General-purpose OS	p. 3
2.1 PicoRadio II Protocol Design	p. 3
2.2 General-purpose Multi-tasking OS	p. 4
2.3 Event-driven OS	p. 8
2.4 Comparison Summary	p. 9
3 Low Power Reactive OS for Heterogeneous Architectures	p. 12
3.1 Event-driven Global Scheduler and Power Management	p. 12
3.2 TinyOS Limitations and Proposed Extensions	p. 14
4 Conclusion and Future Work	p. 15
References	p. 16
2 A Modified Dual-Priority Scheduling Algorithm for Hard Real-Time Systems to Improve Energy Savings	p. 17
1 Introduction	p. 17
2 Dual-Priority Scheduling	p. 19
3 Power-Low Modified Dual-Priority Scheduling	p. 21
4 Experimental Results	p. 28
5 Summary	p. 36
References	p. 36
3 Toward the Placement of Power Management Points in Real-Time Applications	p. 37
1 Introduction	p. 37
2 Model	p. 39
3 Sources of Overhead	p. 40
3.1 Computing the New Speed	p. 40
3.2 Setting the New Speed	p. 40
4 Speed Adjustment Schemes	p. 41
4.1 Proportional Dynamic Power Management	p. 41
4.2 Dynamic Greedy Power Management	p. 42
4.3 Evaluation of Power Management Schemes	p. 43
5 Optimal Number of PMPs	p. 44
5.1 Evaluation of the Analytical Model	p. 45
6 Conclusion	p. 48
Appendix Derivation of Formulas	p. 48
References	p. 51
4 Energy Characterization of Embedded Real-Time Operating Systems	p. 53
1 Introduction	p. 53
2 Related Work	p. 55
3 System Overview	p. 56
3.1 The Hardware Platform	p. 56
3.2 RTOS overview	p. 57
4 Characterization Strategy	p. 59
5 RTOS Characterization Results	p. 60
5.1 Kernel Services	p. 60
5.2 I/O Drivers	p. 62
5.2.1 Burstiness Test	p. 62
5.2.2 Clock Speed Test	p. 63
5.2.3 Resource Contention Test	p. 64
5.3 Application Example: RTOS vs Stand-alone	p. 65
5.4 Cache Related Effects in Thread Switching	p. 66
6 Summary of Findings	p. 66
7 Conclusions	p. 67
References	p. 72
5 Dynamic Cluster Reconfiguration for Power and Performance	p. 75
1 Motivation	p. 77
2 Cluster Configuration and Load Distribution	p. 78
2.1 Overview	p. 78
2.2 Implementations	p. 81
3 Methodology	p. 83
4 Experimental Results	p. 84
5 Related Work	p. 89
6 Conclusions	p. 91
References	p. 91
6 Energy Management of Virtual Memory on Diskless Devices	p. 95
1 Introduction	p. 96
2 Related Work	p. 97
3 Problem Formulation	p. 98
4 EEL[subscript RM] Prototype Compiler	p. 100
4.1 Phase 1 - Analysis	p. 100
4.2 Phase 2 - Code Generation	p. 101
4.3 Performance Model	p. 102
4.4 Example	p. 102
4.5 Implementation Issues	p. 103
5 Experiments	p. 105
5.1 Benchmark Characteristics	p. 106
5.2 Simulation Results	p. 107
6 Future Work	p. 110
7 Conclusion	p. 111
References	p. 111
7 Propagating Constants Past Software to Hardware Peripherals on Fixed-Application Embedded Systems	p. 115
1 Introduction	p. 116
2 Example	p. 119
3 Parameters in Cores	p. 120
4 Propagating Constants from Software to Hardware	p. 123
5 Experiments	p. 125
5.1 8255A Programmable Peripheral Interface	p. 126
5.2 8237A DMA Controller	p. 127
5.3 PC16550A UART	p. 128
5.4 Free-DCT-L Core	p. 128
5.5 Results	p. 131
6 Future Work	p. 133
7 Conclusions	p. 134
References	p. 134
8 Constructive Timing Violation for Improving Energy Efficiency	p. 137
1 Introduction	p. 137
2 Low Power via Fault-Tolerance	p. 139
3 Evaluation Methodology	p. 143
4 Simulation Results	p. 143
5 Related Work	p. 147
6 Conclusion and Future Work	p. 151
References	p. 151
9 Power Modeling and Reduction of VLIW Processors	p. 155
1 Introduction	p. 155
2 Cycle-Accurate VLIW Power Simulation	p. 156
2.1 IMPACT Architecture Framework	p. 156
2.2 Power Models	p. 157
2.3 PowerImpact	p. 158
3 Clock Ramping	p. 159
3.1 Clock Ramping with Hardware Prescan (CRHP)	p. 160
3.2 Clock Ramping with Compiler-based Prediction (CRCP)	p. 162
3.2.1 Basic CRCP Algorithm	p. 162
3.2.2 Reduction of Redundant Ramp-up Instructions	p. 164
3.2.3 Control Flow	p. 165
3.2.4 Load Instructions	p. 165
4 Experimental Results	p. 165
5 Conclusions and Discussion	p. 169
References	p. 170
10 Low-Power Design of Turbo Decoder with Exploration of Energy-Throughput Trade-off	p. 173
1 Introduction	p. 173
2 Data Transfer and Storage Exploration Methodology	p. 176
3 Global Data Flow and Loop Transformations	p. 178
3.1 Removal of Interleaver Memory	p. 178
3.2 Enabling Parallelism	p. 179
4 Storage Cycle Budget Distribution	p. 180
4.1 Memory Hierarchy Layer Assignment	p. 181
4.2 Data Restructuring	p. 182
4.3 Loop Transformations for Parallelization	p. 183
4.3.1 Loop Merging	p. 183
4.3.2 Loop Pipelining	p. 184
4.3.3 Partial Loop Unrolling	p. 184
4.3.4 Loop Transformation Results	p. 185
4.4 Storage Bandwidth Optimization	p. 185
5 Memory Organization	p. 186
5.1 Memory Organization Exploration	p. 186
5.2 Memory Organization Decision	p. 188
6 Conclusions	p. 190
References	p. 190
11 Static Analysis of Parameterized Loop Nests for Energy Efficient Use of Data Caches	p. 193
1 Introduction	p. 193
2 Energy and Line Size	p. 195
3 Background	p. 195
4 The Parameterized Loop Analysis	p. 197
4.1 Reduction to Single Reference Interference	p. 199
4.2 Interference and Reuse Trade-off	p. 200
5 STAMINA Implementation Results	p. 200
5.1 Swim from SPEC 2000	p. 201
5.2 Self Interference	p. 201
5.3 Tiling and Matrix Multiply	p. 202
6 Summary and Future Work	p. 203
References	p. 203
12 A Fresh Look at Low-Power Mobile Computing	p. 209
1 Introduction	p. 209
2 Architecture	p. 211
3 Handover and the Quantization of Computational Resources	p. 212
3.1 Standardization of Execution Environment's Parameters	p. 214
3.2 A Commercial Vision: Impact on Billing, Customer Loyalty and Churn	p. 215
4 Segmentation of Functionality: The XU-MS Split	p. 215
4.1 Use of Field-Programmable Hardware in the Mobile Station	p. 217
4.2 Special End-To-End Application Requirements	p. 217
5 Status and Research Vision	p. 218
References	p. 219
Index	p. 221

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