Oversampled delta-sigma modulators : analysis, applications and novel topologies

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Title:

Personal Author:

Kozak, Mucahit

Publication Information:

Dordrecht : Kluwer Academic Pubs, 2003

ISBN:

9781402074202

Subject Term:

Analog-to-digital converters -- Design and construction

Modulators (Electronics) -- Design and construction

Added Author:

Kale, Izzet

Available:*

Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010046811	TK7887.6 K69 2003	Open Access Book	Book	Searching... Unknown

Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies presents theorems and their mathematical proofs for the exact analysis of the quantization noise in delta-sigma modulators. Extensive mathematical equations are included throughout the book to analyze both single-stage and multi-stage architectures. It has been proved that appropriately set initial conditions generate tone free output, provided that the modulator order is at least three. These results are applied to the design of a Fractional-N PLL frequency synthesizer to produce spurious free RF waveforms. Furthermore, the book also presents time-interleaved topologies to increase the conversion bandwidth of delta-sigma modulators. The topologies have been generalized for any interleaving number and modulator order.
The book is full of design and analysis techniques and contains sufficient detail that enables readers with little background in the subject to easily follow the material in it.

Author Notes

Mucahit Kozak University of Rochester, USA
Izzet Kale University of Westminster, UK

Preface	p. xi
1. Introduction	p. 1
1.1 Aims and Motivations	p. 1
1.2 Original Contributions	p. 4
1.3 Outline of the Research Monograph	p. 5
2. Basic Principles of Delta-Sigma Modulation	p. 7
2.1 Nyquist Rate Converters	p. 8
2.2 Quantization Noise	p. 10
2.3 Oversampling Advantage	p. 13
2.4 [Delta Sigma] Modulation	p. 15
2.5 Limit Cycle Oscillations and Tones	p. 21
2.5.1 Dithering	p. 21
2.5.2 Chaotic [Delta Sigma] Modulators	p. 23
2.6 Higher-order [Delta Sigma] Modulators	p. 23
2.6.1 Single-stage Architectures	p. 24
2.6.2 Multi-stage Architectures	p. 25
2.7 Multi-bit [Delta Sigma] Converters	p. 27
2.8 State-of-the-art Analysis	p. 28
3. Analysis of Mash Delta-Sigma Modulators with DC Inputs	p. 31
3.1 Introduction	p. 32
3.2 Non-linear Difference Equations	p. 35
3.2.1 First-order [Delta Sigma] Modulator	p. 35
3.2.2 Higher-order MASH [Delta Sigma] Modulator	p. 40
3.3 Statistics of the Quantizer Error Sequence	p. 43
3.3.1 Preliminaries	p. 43
3.3.2 First-order [Delta Sigma] Modulator	p. 45
3.3.3 Higher-order MASH [Delta Sigma] Modulator	p. 52
3.4 Simulation Results	p. 62
3.5 Output Spectrum	p. 70
3.6 Digital Realization of Irrational Initial Condition	p. 71
3.7 Conclusion	p. 74
4. Analysis of Single-Stage Delta-Sigma Modulators with DC Inputs	p. 79
4.1 Motivation behind the Work	p. 79
4.2 Uniform Quantizer in the No-Overload Region	p. 80
4.3 Non-linear Difference Equations	p. 83
4.3.1 Second-order [Delta Sigma] Modulator	p. 83
4.3.2 Higher-order [Delta Sigma] Modulator	p. 86
4.4 No-Overload Stability Criterion	p. 95
4.5 Solution to the Non-linear Difference Equation	p. 99
4.6 Statistics of the Quantizer Error Sequence	p. 106
4.6.1 Second-order [Delta Sigma] Modulator	p. 107
4.6.2 Higher-order [Delta Sigma] Modulator	p. 108
4.7 Fundamental Result	p. 109
4.8 Simulation Results	p. 109
4.9 Output Spectrum	p. 112
4.10 Error-Feedback Topology	p. 116
4.11 Conclusion	p. 118
5. Fractional-N PLL Frequency Synthesizers	p. 119
5.1 Introduction	p. 120
5.2 Analysis of PLLs	p. 121
5.2.1 Small-signal Model	p. 122
5.2.2 Second-order Systems	p. 124
5.2.3 Charge-pump PLL	p. 128
5.3 The Fractional-N Concept	p. 131
5.3.1 First Generation Fractional-N PLL Synthesizers	p. 132
5.3.2 Higher-order [Delta Sigma] Modulation for Modulus Control	p. 134
5.4 Design and Simulation of Fractional-N PLL Frequency Synthesizers	p. 138
5.4.1 Linear Model of the Charge-Pump PLL	p. 138
5.4.2 Design Issues	p. 141
5.4.3 Computer Simulation Model	p. 145
5.4.4 Overall Fractional-N PLL Simulation Results	p. 152
5.5 Pipelined Implementation of Mash [Delta Sigma] Modulators	p. 157
5.6 Conclusion	p. 165
6. Time-Interleaved Delta-Sigma Modulators	p. 167
6.1 Introduction	p. 168
6.2 Block Digital Filtering Approach	p. 170
6.3 Time-Interleaved [Delta Sigma] Modulators with Reduced Complexity	p. 175
6.4 Simulations	p. 182
6.5 Implementation Issues	p. 184
6.5.1 Finite Op-amp Gain	p. 184
6.5.2 Op-amp dc Offset	p. 185
6.5.3 Mismatch Effects	p. 187
6.5.4 Sampling Clock Jitter	p. 190
6.5.5 Critical Delay Problem	p. 190
6.6 Hardware Comparison	p. 192
6.7 Higher-order Time-Interleaved [Delta Sigma] Modulators	p. 194
6.7.1 Cascaded Integrators with Feed-Forward Summation Topology	p. 195
6.7.2 Cascaded Integrators with Distributed Feedback as well as Feed-forward Branch Topology	p. 199
6.7.3 Simulations	p. 201
6.7.4 Coefficient Mismatches	p. 203
6.8 Zero-Insertion Interpolation Time-Interleaving	p. 206
6.9 Further Practical Issues	p. 215
6.9.1 Sampling Clock Jitter Effects	p. 215
6.9.2 Branch Mismatch Effects	p. 217
6.10 Conclusion	p. 218
References	p. 221

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Table of Contents