Reconfigurable computing : accelerating computation with field-programmable gate arrays

Title:

Personal Author:

Gokhale, Maya

Publication Information:

Dordrecht : Springer, 2005

ISBN:

9780387261058

Subject Term:

Adaptive computing systems

Field programmable gate arrays

Added Author:

Graham, Paul S.

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Library	Item Barcode	Call Number	Material Type	Item Category 1	Status
Searching... PSZ JB	30000010099248	QA76.9.A3 G64 2005	Open Access Book	Book	Searching... Unknown

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Summary

A one-of-a-kind survey of the field of Reconfigurable Computing

Gives a comprehensive introduction to a discipline that offers a 10X-100X acceleration of algorithms over microprocessors

Discusses the impact of reconfigurable hardware on a wide range of applications: signal and image processing, network security, bioinformatics, and supercomputing

Includes the history of the field as well as recent advances

Includes an extensive bibliography of primary sources

1 An Introduction to Reconfigurable Computing	p. 1
1.1 What is RC?	p. 1
1.2 RC Architectures	p. 3
1.3 How did RC originate?	p. 4
1.4 Inside the FPGA	p. 6
1.5 Mapping Algorithms to Hardware	p. 7
1.6 RC Applications	p. 8
1.7 Example: Dot Product	p. 9
1.8 Further Reading	p. 10
2 Reconfigurable Logic Devices	p. 11
2.1 Field-Programmable Gate Arrays	p. 12
2.1.1 Basic Architecture	p. 12
2.1.2 Specialized Function Blocks	p. 22
2.1.3 Programming Architecture	p. 26
2.2 Coarse-Grained Reconfigurable Arrays	p. 28
2.2.1 Raw	p. 29
2.2.2 PipeRench	p. 30
2.2.3 RaPiD	p. 32
2.2.4 PACT XPP	p. 33
2.2.5 MathStar	p. 35
2.3 Summary	p. 36
3 Reconfigurable Computing Systems	p. 37
3.1 Parallel Processing on Reconfigurable Computers	p. 37
3.1.1 Instruction Level Parallelism	p. 37
3.1.2 Task Level Parallelism	p. 39
3.2 A Survey of Reconfigurable Computing Systems	p. 41
3.2.1 I/O Bus Accelerator	p. 43
3.2.2 Massively Parallel FPGA array	p. 45
3.2.3 Reconfigurable Supercomputer	p. 45
3.2.4 Reconfigurable Logic Co-processor	p. 47
3.3 Summary	p. 49
4 Language and Compilation	p. 51
4.1 Design Cycle	p. 51
4.2 Languages	p. 54
4.2.1 Algorithmic RC Languages	p. 55
4.2.2 Hardware Description Languages (HDL)	p. 57
4.3 High Level Compilation	p. 60
4.3.1 Compiler Phases	p. 65
4.3.2 Analysis and Optimizations	p. 66
4.3.3 Scheduling	p. 67
4.4 Low Level Design Flow	p. 68
4.4.1 Logic Synthesis	p. 69
4.4.2 Technology Mapping	p. 70
4.4.3 Logic Placement	p. 71
4.4.4 Signal Routing	p. 72
4.4.5 Configuration Bitstreams	p. 73
4.5 Debugging Reconfigurable Computing Applications	p. 74
4.5.1 Basic Needs for Debugging	p. 74
4.5.2 Debugging Facilities	p. 75
4.5.3 Challenges for RC Application Debugging	p. 84
4.6 Summary	p. 85
5 Signal Processing Applications	p. 87
5.1 What is Digital Signal Processing?	p. 87
5.2 Why Use Reconfigurable Computing for DSP?	p. 89
5.2.1 Reconfigurable Computing's Suitability for DSP	p. 89
5.2.2 Comparing DSP Implementation Technologies	p. 92
5.3 DSP Application Building Blocks	p. 96
5.3.1 Basic Operations and Elements	p. 97
5.3.2 Filtering	p. 102
5.3.3 Transforms	p. 103
5.4 Example DSP Applications	p. 108
5.4.1 Beamforming	p. 108
5.4.2 Software Radio	p. 112
5.5 Summary	p. 117
6 Image Processing	p. 119
6.1 RC for Image and Video Processing	p. 119
6.2 Local Neighborhood Functions	p. 121
6.2.1 Cellular Arrays for Pixel Parallelism	p. 123
6.2.2 Image Pipelines for Instruction-Level Parallelism	p. 123
6.3 Convolution	p. 124
6.4 Morphology	p. 125
6.5 Feature Extraction	p. 127
6.6 Automatic Target Recognition	p. 129
6.7 Image Matching	p. 131
6.8 Evolutionary Image Processing	p. 134
6.9 Summary	p. 139
7 Network Security	p. 141
7.1 Cryptographic Applications	p. 141
7.1.1 Cryptography Basics	p. 142
7.1.2 RC Cryptographic Algorithm Implementations	p. 146
7.2 Network Protocol Security	p. 148
7.2.1 RC Network Interface	p. 148
7.2.2 Security Protocols	p. 151
7.2.3 Network Defense	p. 152
7.3 Summary	p. 155
8 Bioinformatics Applications	p. 157
8.1 Introduction	p. 157
8.2 Applications	p. 159
8.2.1 Genome Assembly	p. 159
8.2.2 Content-Based Search	p. 160
8.2.3 Genome Comparison	p. 160
8.2.4 Molecular Phylogeny	p. 161
8.2.5 Pattern Matching	p. 161
8.2.6 Protein Domain Databases	p. 162
8.3 Dynamic Programming Algorithms	p. 163
8.3.1 Alignments	p. 163
8.3.2 Dynamic Programming Equations	p. 164
8.3.3 Gap Functions	p. 166
8.3.4 Systolic DP Computation	p. 166
8.3.5 Backtracking	p. 167
8.3.6 Modulo Encoding	p. 169
8.3.7 FPGA Implementations	p. 170
8.4 Seed-Based Heuristics	p. 170
8.4.1 Filtering, Heuristics, and Quality Values	p. 171
8.4.2 BLAST : a 3-Stages Heuristic	p. 171
8.4.3 Seed Indexing	p. 172
8.4.4 FPGA Implementations	p. 174
8.5 Profiles, HMMs and Language Models	p. 174
8.5.1 Position-Dependent Profiles	p. 174
8.5.2 Hidden Markov Models	p. 175
8.5.3 Language Models	p. 176
8.6 Bioinformatics FPGA Accelerators	p. 177
8.6.1 Splash	p. 178
8.6.2 Perle	p. 178
8.6.3 GenStorm	p. 178
8.6.4 RDisk	p. 178
8.6.5 BioXL/H	p. 181
8.6.6 DeCypher	p. 181
8.7 Summary	p. 181
9 Supercomputing Applications	p. 183
9.1 Introduction	p. 183
9.2 Monte Carlo Simulation of Radiative Heat Transfer	p. 184
9.2.1 Algorithm Description	p. 185
9.2.2 Hardware Implementation	p. 187
9.2.3 Performance	p. 188
9.3 Urban Road Traffic Simulation	p. 192
9.3.1 CA Traffic Modeling	p. 193
9.3.2 Intersections and Global Behavior	p. 194
9.3.3 Constructive Approach	p. 196
9.3.4 Streaming Approach	p. 198
9.4 Summary	p. 202
References	p. 205
Index	p. 233

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Table of Contents