Cover image for Splash 2 : FPGAs in custom computing machine
Title:
Splash 2 : FPGAs in custom computing machine
Publication Information:
Los Alamitos, Calif. : IEEE Computer Society Press, 1996
ISBN:
9780818674136

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30000010058228 QA76.8.S65 B83 1996 Open Access Book Book
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Summary

Summary

This book describes the Splash 2 computing system as designed and built at the Supercomputing Research Center. This is a novel attached processor using Xilinx 4010 FPGAs as its processing elements and whose application programming language is VHDL. This is the first publication that details the complete Splash 2 project -- the hardware and software systems, the architecture and their implementations, and the design process by which the architecture evolved from an earlier version machine. This text allows you to understand why the machine has been engineered in the way it has. In addition to the description of the machine, several applications are described in detail, permitting the reader to gain an understanding of the capabilities and the limitations of this kind of computing device.

The Splash 2 program is significant for two reasons. First, Splash 2 is part of a complete computer system that achieves supercomputer like performance on a number of different applications. The second significant aspect is that this large system is capable of performing real computations on real problems. In order to understand what happens when the application programmer is permitted to design the processor architecture of the machine that execute his programs, it is necessary to see the system as a whole. This book looks in-depth at one of the handful of data points in the design space of this new kind of machine.


Author Notes

Duncan A. Buell NCR Professor of Computer Science and Engineering Dept. of Computer Science and E University of South Carolina.


Table of Contents

Prefacep. xi
1 Custom Computing Machines: an Introductionp. 1
1.1 Introductionp. 1
1.2 The Context for Splash 2p. 4
1.2.1 FPGAsp. 4
1.2.2 Architecturep. 5
1.2.3 Programmingp. 6
2 The Architecture of Splash 2p. 10
2.1 Introductionp. 10
2.2 The Building Blocksp. 11
2.3 The System Architecturep. 12
2.4 Data Pathsp. 13
2.5 The Splash 2 Array Boardp. 16
2.5.1 The Linear Arrayp. 16
2.5.2 The Splash 2 Crossbarp. 16
2.5.3 Xilinx Chip X0 and Broadcast Modep. 17
2.6 The Interface Board and Control Featuresp. 17
3 Hardware Implementationp. 19
3.1 Introductionp. 19
3.2 Development Board Designp. 21
3.3 Interface Board Designp. 21
3.3.1 DMA Channelp. 23
3.3.2 XL and XRp. 23
3.3.3 Interruptsp. 24
3.3.4 Clockp. 24
3.3.5 Programming and Readbackp. 24
3.3.6 Miscellaneous Registersp. 25
3.4 Array Board Designp. 25
3.4.1 Processing Elementp. 26
3.4.2 Control Elementp. 28
3.4.3 External Memory Accessp. 28
3.4.4 Crossbarp. 28
3.4.5 Programming and Readbackp. 29
3.4.6 Miscellaneous Registersp. 29
4 Splash 2: the Evolution of a New Architecturep. 31
4.1 Splash 1p. 31
4.2 Splash 2: Thoughts on a Redesignp. 34
4.3 Programming Languagep. 36
4.4 Choice of FPGAsp. 37
4.5 Choice of Host and Busp. 38
4.6 Chip-to-Chip Interconnectionsp. 39
4.7 Multitaskingp. 42
4.8 Chip X0 and Broadcastp. 43
4.9 Other Design Decisionsp. 43
5 Software Architecturep. 46
5.1 Introductionp. 46
5.2 Backgroundp. 47
5.3 VHDL as a Programming Languagep. 49
5.3.1 History and Purpose of VHDLp. 50
5.3.2 VHDL Language Featuresp. 50
5.3.3 Problems with VHDLp. 51
5.4 Software Environmentp. 51
5.5 Programmer's View of Splash 2p. 55
5.5.1 Programming Processp. 55
5.5.2 Processing Element Viewp. 56
5.5.3 Interface Board Viewp. 57
5.5.4 Host Viewp. 57
6 Software Implementationp. 60
6.1 Introductionp. 60
6.2 VHDL Environmentp. 60
6.2.1 Splash 2 VHDL Libraryp. 61
6.2.2 Standard Entity Declarationsp. 61
6.2.3 Programming Stylep. 64
6.3 Splash 2 Simulatorp. 66
6.3.1 Structurep. 66
6.3.2 Configuring the Simulatorp. 67
6.3.3 Input and Outputp. 68
6.3.4 Crossbar and Memory Modelsp. 68
6.3.5 Hardware Constraintsp. 70
6.4 Compilationp. 70
6.4.1 Logic Synthesisp. 70
6.4.2 Physical Mappingp. 71
6.4.3 Debugging Supportp. 71
6.5 Runtime Systemp. 72
6.5.1 T2: A Symbolic Debuggerp. 72
6.5.2 Runtime Libraryp. 73
6.5.3 Device Driverp. 74
6.6 Diagnosticsp. 75
7 A Data Parallel Programming Modelp. 77
7.1 Introductionp. 78
7.2 Data-parallel Bit Cp. 80
7.2.1 dbC Overviewp. 80
7.2.2 dbC Examplep. 81
7.3 Compiling from dbC to Splash 2p. 82
7.3.1 Creating a Specialized SIMD Enginep. 83
7.3.2 Generic SIMD Codep. 84
7.3.3 Generating VHDLp. 84
7.4 Global Operationsp. 88
7.4.1 Nearest-Neighbor Communicationp. 88
7.4.2 Reduction Operationsp. 89
7.4.3 Host/Processor Communicationp. 91
7.5 Optimization: Macro Instructionsp. 92
7.5.1 Creating a Macro Instructionp. 93
7.5.2 Discussionp. 94
7.6 Evaluation: Genetic Database Searchp. 94
7.7 Conclusions and Future Workp. 95
8 Searching Genetic Databases on Splash 2p. 97
8.1 Introductionp. 97
8.1.1 Edit Distancep. 98
8.1.2 Dynamic Programming Algorithmp. 98
8.2 Systolic Sequence Comparisonp. 100
8.2.1 Bidirectional Arrayp. 100
8.2.2 Unidirectional Arrayp. 103
8.3 Implementationp. 104
8.3.1 Modular Encodingp. 105
8.3.2 Configurable Parametersp. 106
8.3.3 Bidirectional Arrayp. 107
8.3.4 Unidirectional Arrayp. 107
8.4 Benchmarksp. 107
8.5 Discussionp. 108
8.6 Conclusionsp. 108
9 Text Searching on Splash 2p. 110
9.1 Introductionp. 110
9.2 The Text Searching Algorithmp. 111
9.3 Description of the Single-Byte Splash Programp. 113
9.4 Timings, Discussionp. 114
9.5 Outline of the 16-bit Approachp. 115
9.6 Conclusionsp. 116
10 Fingerprint Matching on Splash 2p. 117
10.1 Introductionp. 117
10.2 Backgroundp. 120
10.2.1 Pattern Recognition Systemsp. 121
10.2.2 Terminologyp. 122
10.2.3 Stages in AFISp. 123
10.3 Splash 2 Architecture and Programming Modelsp. 125
10.4 Fingerprint Matching Algorithmp. 125
10.4.1 Minutia Matchingp. 126
10.4.2 Matching Algorithmp. 127
10.5 Parallel Matching Algorithmp. 128
10.5.1 Preprocessing on the Hostp. 131
10.5.2 Computations on Splashp. 132
10.5.3 VHDL Specification for X0p. 133
10.6 Simulation and Synthesis Resultsp. 134
10.7 Execution on Splash 2p. 137
10.7.1 User Interfacep. 137
10.7.2 Performance Analysisp. 137
10.8 Conclusionsp. 139
11 High-Speed Image Processing With Splash 2p. 141
11.1 Introductionp. 141
11.2 The VTSplash Systemp. 142
11.3 Image Processing Terminology and Architectural Issuesp. 143
11.4 Case Study: Median Filteringp. 150
11.5 Case Study: Image Pyramid Generationp. 153
11.5.1 Gaussian Pyramidp. 154
11.5.2 Two Implementations for Gaussian Pyramid on Splash 2p. 155
11.5.3 The Hybrid Pipeline Gaussian Pyramid Structurep. 157
11.5.4 The Laplacian Pyramidp. 157
11.5.5 Implementation of the Laplacian Pyramid on Splash 2p. 159
11.6 Performancep. 159
11.7 Summaryp. 163
12 The Promise and the Problemsp. 166
12.1 Some Bottom-Line Conclusionsp. 166
12.1.1 High Bandwidth I/O Is a Mustp. 166
12.1.2 Memory Is a Mustp. 167
12.1.3 Programming Is Possible, and Becoming More Sop. 168
12.1.4 The Programming Environment Is Crucialp. 168
12.2 To Where from Here?p. 169
12.3 If Not Splash 3, Then What?p. 171
12.3.1 Architecturesp. 172
12.3.2 Custom Processorsp. 173
12.3.3 Languagesp. 174
12.4 The "Killer" Applicationsp. 177
12.5 Final Wordsp. 178
A Splash 2 Development--The Project Manager's Summaryp. 179
B An Example Applicationp. 186
Referencesp. 190