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Cover image for Metamodeling-driven IP reuse for SoC integration and microprocessor design
Title:
Metamodeling-driven IP reuse for SoC integration and microprocessor design
Personal Author:
Publication Information:
Boston : Artech House, c2009
Physical Description:
xxi, 287 p. : ill. ; 24 cm.
ISBN:
9781596934245
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Item Category 1
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30000010236039 QA76.76.R47 M328 2009 Open Access Book Book
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Summary

Summary

Offers an understanding of metamodeling approaches for the reuse of intellectual properties (IPs) in the form of design or verification components. This book covers the issues associated with fast and effective integration of reusable design components into a system-on-a-chip (SoC) to achieve faster design turn-around time.


Author Notes

Deepak A. Mathaikutty works in the Microarchitecture Research Laboratory at Intel Corporation. He holds an M.S. and a Ph.D. in computer engineering from the Virginia Polytechnic Institute and State University.
Sandeep K. Shukla is an associate professor at the Virginia Polytechnic Institute and State University. He holds an M.S. and a Ph.D. in computer science from the State University of New York at Albany.


Table of Contents

Prefacep. xi
Acknowledgmentsp. xxi
Chapter 1 Introductionp. 1
1.1 Ongoing Efforts in Design IP Reusep. 5
1.2 Ongoing Efforts in Verification IP Reusep. 8
1.3 Essential Issues with IP Reusep. 9
1.4 Metamodeling Approach to Reusep. 13
1.5 Problem Statementp. 15
1.6 Research Contributionsp. 17
1.7 Tools and Techniques Developedp. 18
Referencesp. 19
Chapter 2 Backgroundp. 23
2.1 Metamodelingp. 23
2.1.1 Implicit Metamodeling Versus Explicit Metamodelingp. 25
2.1.2 Generic Modeling Environmentp. 26
2.2 Component Composition Frameworkp. 28
2.3 Reflection and Introspection (R-I)p. 30
2.4 SystemCp. 31
2.5 Model-Driven Validationp. 32
2.5.1 Microprocessor Validation Flowp. 32
2.5.2 Simulation-Based Functional Validationp. 35
2.6 Test Generationp. 36
2.6.1 Constraint Programmingp. 36
2.6.2 Esterel Studiop. 37
2.7 Coverage-Directed Test Generationp. 38
2.7.1 Structural Coveragep. 38
2.7.2 Functional Coveragep. 40
2.7.3 Property Specification Language (PSL)p. 41
2.7.4 Fault Classificationp. 41
Referencesp. 42
Chapter 3 Related Workp. 45
3.1 Component Composition Frameworkp. 45
3.1.1 The BALBOA Frameworkp. 45
3.1.2 Liberty Simulation Environment (LSE)p. 46
3.1.3 EWDp. 47
3.1.4 Ptolemy IIp. 47
3.1.5 Metropolisp. 48
3.2 Component-Based Software Design Environmentsp. 49
3.3 IP Interfacing Standardsp. 50
3.3.1 SPIRITp. 51
3.4 Existing Tools for Structural Reflectionp. 51
3.5 Architecture Description Languagesp. 53
3.6 Test Generationp. 54
Referencesp. 56
I Design Reusep. 61
Chapter 4 A Metamodel for Component Compositionp. 63
4.1 CC Language, Metamodel, and Modelp. 65
4.1.1 Component Composition Language (CCL)p. 65
4.1.2 Component Composition Metamodel (CCMM)p. 68
4.1.3 Component Composition Model (CCM)p. 77
4.2 CC Analysis and Translationp. 82
4.2.1 Consistency Checkingp. 82
4.2.2 Type Inferencep. 83
4.2.3 XML Translationp. 93
4.3 Case Studiesp. 94
4.3.1 AMBA AHB RTL Bus Modelp. 94
4.3.2 Simple Bus TL Modelp. 97
4.4 Design Experience and Summaryp. 100
Referencesp. 101
Chapter 5 IP Reflection and Selectionp. 103
5.1 Metadata for IP Compositionp. 104
5.2 Metadata on a SystemC IP Specificationp. 105
5.3 Tools and Methodologyp. 113
5.3.1 Stage 1: SystemC Parsingp. 114
5.3.2 Stage 2: AST Parsing and DOM Populationp. 114
5.3.3 Stage 3: Processing and Constraining DOMp. 118
5.4 IP Selectionp. 123
5.4.1 Illustrative Examplep. 130
5.5 Case Studyp. 131
5.6 Summaryp. 134
Referencesp. 135
Chapter 6 Typing Problems in IP Compositionp. 137
6.1 MCF Type Definitionsp. 138
6.1.1 Component Composition Languagep. 139
6.1.2 IP Libraryp. 144
6.2 Type Resolution in MCFp. 145
6.2.1 Type Inference on Architectural Templatep. 146
6.2.2 Type Substitution Using IP Libraryp. 149
6.3 Comparative Studyp. 156
6.4 Case Studyp. 157
6.5 Summaryp. 161
Referencesp. 161
Chapter 7 IP Compositionp. 163
7.1 MCF Ingredientsp. 166
7.2 Handling Generic IPsp. 168
7.3 Interaction Patternp. 170
7.3.1 Interaction Consolep. 172
7.4 Case Studyp. 174
7.5 Summaryp. 178
Referencesp. 178
Chapter 8 Checker Generation for IP Verificationp. 181
8.1 Enhanced Design Flowp. 181
8.2 Enhanced Modeling Frameworkp. 183
8.2.1 Component Propertiesp. 185
8.2.2 Composition Propertiesp. 185
8.2.3 XML Translationp. 186
8.3 Interaction Consolep. 187
8.4 Conclusionp. 191
Referencesp. 191
II Verification Reusep. 193
Chapter 9 A Metamodel for Microprocessorsp. 195
9.1 Modeling and Validation Environment (MMV)p. 195
9.1.1 System-Level View (SV)p. 197
9.1.2 Architecture View (AV)p. 201
9.1.3 Microarchitecture View (MV)p. 207
9.2 Simulator Generationp. 212
9.2.1 Metamodel Additions for Simulator Generationp. 213
9.2.2 ALGS Generationp. 214
9.3 Test Generationp. 221
9.3.1 CSP Formulation for Generating Random Test Casesp. 221
9.4 Case Study: Modeling Vespa in MMVp. 224
9.4.1 System-Level Modelp. 225
9.4.2 Architecture Modelp. 228
9.4.3 Refinement of Real-Time Software Schedulerp. 230
9.4.4 Microarchitecture Modelp. 232
9.5 Summaryp. 234
Referencesp. 235
Chapter 10 Design Fault Directed Test Generationp. 237
10.1 Motivationp. 238
10.2 Modeling and Test Generationp. 240
10.2.1 Architecture Modelingp. 240
10.2.2 Microarchitecture Modelingp. 240
10.2.3 CSP Formulationp. 242
10.2.4 Test Case Generator (TCG)p. 244
10.2.5 Usage Modep. 245
10.3 Coverage Constraintsp. 246
10.3.1 Statement Coveragep. 246
10.3.2 Branch Coveragep. 247
10.3.3 MCDCp. 248
10.3.4 Design Fault Coveragep. 249
10.4 Resultsp. 251
10.5 Summaryp. 252
Referencesp. 253
Chapter 11 Model-Driven System-Level Validationp. 255
11.1 Test Generation Methodologyp. 256
11.1.1 Modeling and Simulation and Verificationp. 256
11.1.2 Coverage Annotationp. 261
11.1.3 Test Generationp. 264
11.2 SystemC Validationp. 266
11.2.1 TestSpec Generator (TSG)p. 268
11.3 Case Studyp. 269
11.3.1 PSM Specificationp. 269
11.3.2 Functional Modelp. 271
11.3.3 Verification Modelp. 271
11.3.4 Coverage Annotationp. 271
11.3.5 Test Generationp. 272
11.3.6 Implementation Modelp. 272
11.4 Summaryp. 273
Referencesp. 273
Chapter 12 Conclusion and Future Workp. 275
12.1 Summaryp. 275
12.2 Future Workp. 278
12.2.1 Solution Methodology Enhancementsp. 278
12.2.2 Extensions for Industry Recognitionp. 279
Referencesp. 281
About the Authorsp. 285
Indexp. 287
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