Title:
Metamodeling-driven IP reuse for SoC integration and microprocessor design
Personal Author:
Publication Information:
Boston : Artech House, c2009
Physical Description:
xxi, 287 p. : ill. ; 24 cm.
ISBN:
9781596934245
Added Author:
Available:*
Library | Item Barcode | Call Number | Material Type | Item Category 1 | Status |
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Searching... | 30000010236039 | QA76.76.R47 M328 2009 | Open Access Book | Book | Searching... |
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Summary
Summary
Offers an understanding of metamodeling approaches for the reuse of intellectual properties (IPs) in the form of design or verification components. This book covers the issues associated with fast and effective integration of reusable design components into a system-on-a-chip (SoC) to achieve faster design turn-around time.
Author Notes
Deepak A. Mathaikutty works in the Microarchitecture Research Laboratory at Intel Corporation. He holds an M.S. and a Ph.D. in computer engineering from the Virginia Polytechnic Institute and State University.
Sandeep K. Shukla is an associate professor at the Virginia Polytechnic Institute and State University. He holds an M.S. and a Ph.D. in computer science from the State University of New York at Albany.
Table of Contents
Preface | p. xi |
Acknowledgments | p. xxi |
Chapter 1 Introduction | p. 1 |
1.1 Ongoing Efforts in Design IP Reuse | p. 5 |
1.2 Ongoing Efforts in Verification IP Reuse | p. 8 |
1.3 Essential Issues with IP Reuse | p. 9 |
1.4 Metamodeling Approach to Reuse | p. 13 |
1.5 Problem Statement | p. 15 |
1.6 Research Contributions | p. 17 |
1.7 Tools and Techniques Developed | p. 18 |
References | p. 19 |
Chapter 2 Background | p. 23 |
2.1 Metamodeling | p. 23 |
2.1.1 Implicit Metamodeling Versus Explicit Metamodeling | p. 25 |
2.1.2 Generic Modeling Environment | p. 26 |
2.2 Component Composition Framework | p. 28 |
2.3 Reflection and Introspection (R-I) | p. 30 |
2.4 SystemC | p. 31 |
2.5 Model-Driven Validation | p. 32 |
2.5.1 Microprocessor Validation Flow | p. 32 |
2.5.2 Simulation-Based Functional Validation | p. 35 |
2.6 Test Generation | p. 36 |
2.6.1 Constraint Programming | p. 36 |
2.6.2 Esterel Studio | p. 37 |
2.7 Coverage-Directed Test Generation | p. 38 |
2.7.1 Structural Coverage | p. 38 |
2.7.2 Functional Coverage | p. 40 |
2.7.3 Property Specification Language (PSL) | p. 41 |
2.7.4 Fault Classification | p. 41 |
References | p. 42 |
Chapter 3 Related Work | p. 45 |
3.1 Component Composition Framework | p. 45 |
3.1.1 The BALBOA Framework | p. 45 |
3.1.2 Liberty Simulation Environment (LSE) | p. 46 |
3.1.3 EWD | p. 47 |
3.1.4 Ptolemy II | p. 47 |
3.1.5 Metropolis | p. 48 |
3.2 Component-Based Software Design Environments | p. 49 |
3.3 IP Interfacing Standards | p. 50 |
3.3.1 SPIRIT | p. 51 |
3.4 Existing Tools for Structural Reflection | p. 51 |
3.5 Architecture Description Languages | p. 53 |
3.6 Test Generation | p. 54 |
References | p. 56 |
I Design Reuse | p. 61 |
Chapter 4 A Metamodel for Component Composition | p. 63 |
4.1 CC Language, Metamodel, and Model | p. 65 |
4.1.1 Component Composition Language (CCL) | p. 65 |
4.1.2 Component Composition Metamodel (CCMM) | p. 68 |
4.1.3 Component Composition Model (CCM) | p. 77 |
4.2 CC Analysis and Translation | p. 82 |
4.2.1 Consistency Checking | p. 82 |
4.2.2 Type Inference | p. 83 |
4.2.3 XML Translation | p. 93 |
4.3 Case Studies | p. 94 |
4.3.1 AMBA AHB RTL Bus Model | p. 94 |
4.3.2 Simple Bus TL Model | p. 97 |
4.4 Design Experience and Summary | p. 100 |
References | p. 101 |
Chapter 5 IP Reflection and Selection | p. 103 |
5.1 Metadata for IP Composition | p. 104 |
5.2 Metadata on a SystemC IP Specification | p. 105 |
5.3 Tools and Methodology | p. 113 |
5.3.1 Stage 1: SystemC Parsing | p. 114 |
5.3.2 Stage 2: AST Parsing and DOM Population | p. 114 |
5.3.3 Stage 3: Processing and Constraining DOM | p. 118 |
5.4 IP Selection | p. 123 |
5.4.1 Illustrative Example | p. 130 |
5.5 Case Study | p. 131 |
5.6 Summary | p. 134 |
References | p. 135 |
Chapter 6 Typing Problems in IP Composition | p. 137 |
6.1 MCF Type Definitions | p. 138 |
6.1.1 Component Composition Language | p. 139 |
6.1.2 IP Library | p. 144 |
6.2 Type Resolution in MCF | p. 145 |
6.2.1 Type Inference on Architectural Template | p. 146 |
6.2.2 Type Substitution Using IP Library | p. 149 |
6.3 Comparative Study | p. 156 |
6.4 Case Study | p. 157 |
6.5 Summary | p. 161 |
References | p. 161 |
Chapter 7 IP Composition | p. 163 |
7.1 MCF Ingredients | p. 166 |
7.2 Handling Generic IPs | p. 168 |
7.3 Interaction Pattern | p. 170 |
7.3.1 Interaction Console | p. 172 |
7.4 Case Study | p. 174 |
7.5 Summary | p. 178 |
References | p. 178 |
Chapter 8 Checker Generation for IP Verification | p. 181 |
8.1 Enhanced Design Flow | p. 181 |
8.2 Enhanced Modeling Framework | p. 183 |
8.2.1 Component Properties | p. 185 |
8.2.2 Composition Properties | p. 185 |
8.2.3 XML Translation | p. 186 |
8.3 Interaction Console | p. 187 |
8.4 Conclusion | p. 191 |
References | p. 191 |
II Verification Reuse | p. 193 |
Chapter 9 A Metamodel for Microprocessors | p. 195 |
9.1 Modeling and Validation Environment (MMV) | p. 195 |
9.1.1 System-Level View (SV) | p. 197 |
9.1.2 Architecture View (AV) | p. 201 |
9.1.3 Microarchitecture View (MV) | p. 207 |
9.2 Simulator Generation | p. 212 |
9.2.1 Metamodel Additions for Simulator Generation | p. 213 |
9.2.2 ALGS Generation | p. 214 |
9.3 Test Generation | p. 221 |
9.3.1 CSP Formulation for Generating Random Test Cases | p. 221 |
9.4 Case Study: Modeling Vespa in MMV | p. 224 |
9.4.1 System-Level Model | p. 225 |
9.4.2 Architecture Model | p. 228 |
9.4.3 Refinement of Real-Time Software Scheduler | p. 230 |
9.4.4 Microarchitecture Model | p. 232 |
9.5 Summary | p. 234 |
References | p. 235 |
Chapter 10 Design Fault Directed Test Generation | p. 237 |
10.1 Motivation | p. 238 |
10.2 Modeling and Test Generation | p. 240 |
10.2.1 Architecture Modeling | p. 240 |
10.2.2 Microarchitecture Modeling | p. 240 |
10.2.3 CSP Formulation | p. 242 |
10.2.4 Test Case Generator (TCG) | p. 244 |
10.2.5 Usage Mode | p. 245 |
10.3 Coverage Constraints | p. 246 |
10.3.1 Statement Coverage | p. 246 |
10.3.2 Branch Coverage | p. 247 |
10.3.3 MCDC | p. 248 |
10.3.4 Design Fault Coverage | p. 249 |
10.4 Results | p. 251 |
10.5 Summary | p. 252 |
References | p. 253 |
Chapter 11 Model-Driven System-Level Validation | p. 255 |
11.1 Test Generation Methodology | p. 256 |
11.1.1 Modeling and Simulation and Verification | p. 256 |
11.1.2 Coverage Annotation | p. 261 |
11.1.3 Test Generation | p. 264 |
11.2 SystemC Validation | p. 266 |
11.2.1 TestSpec Generator (TSG) | p. 268 |
11.3 Case Study | p. 269 |
11.3.1 PSM Specification | p. 269 |
11.3.2 Functional Model | p. 271 |
11.3.3 Verification Model | p. 271 |
11.3.4 Coverage Annotation | p. 271 |
11.3.5 Test Generation | p. 272 |
11.3.6 Implementation Model | p. 272 |
11.4 Summary | p. 273 |
References | p. 273 |
Chapter 12 Conclusion and Future Work | p. 275 |
12.1 Summary | p. 275 |
12.2 Future Work | p. 278 |
12.2.1 Solution Methodology Enhancements | p. 278 |
12.2.2 Extensions for Industry Recognition | p. 279 |
References | p. 281 |
About the Authors | p. 285 |
Index | p. 287 |