Dependability in electronic systems : mitigation of hardware failures, soft errors, and electro-magnetic disturbances

This book covers the practical application of dependable electronic systems in real industry, such as space, train control and automotive control systems, and network servers/routers. The impact from intermittent errors caused by environmental radiation (neutrons and alpha particles) and EMI (Electro-Magnetic Interference) are introduced together with their most advanced countermeasures. Power Integration is included as one of the most important bases of dependability in electronic systems. Fundamental technical background is provided, along with practical design examples.Readers will obtain an overall picture of dependability from failure causes to countermeasures for their relevant systems or products, and therefore, will be able to select the best choice for maximum dependability.

1 Introduction	p. 1
1.1 Trends in Failure Cause and Countermeasure	p. 1
1.2 Contents and Organization of This Book	p. 3
1.3 For the Best Result	p. 5
References	p. 5
2 Terrestrial Neutron-Induced Failures in Semiconductor Devices and Relevant Systems and Their Mitigation Techniques	p. 7
2.1 Introduction	p. 7
2.1.1 SER in Memory Devices	p. 7
2.1.2 MCU in Memory Devices	p. 8
2.1.3 SET and MNU in Logic Devices	p. 8
2.1.4 Chip/System-Level SER Problem: SER Estimation and Mitigation	p. 9
2.1.5 Scope of This Chapter	p. 9
2.2 Basic Knowledge on Terrestrial Neutron-Induced Soft-Error in MOSFET Devices	p. 10
2.2.1 Cosmic Rays from the Outer Space	p. 10
2.2.2 Nuclear Spallation Reaction and Charge Collection in CMOSFET Device	p. 11
2.3 Experimental Techniques to Quantify Soft-Error Rate (SER) and Their Standardization	p. 12
2.3.1 The System to Quantify SER - SECIS	p. 12
2.3.2 Basic Method in JESD89A	p. 13
2.3.3 SEE Classification Techniques in Time Domain	p. 15
2.3.4 MCU Classification Techniques in Topological Space Domain	p. 16
2.4 Evolution of Multi-node Upset Problem	p. 17
2.4.1 MCU Characterization by Accelerator-Based Experiments	p. 17
2.4.2 Multi-coupled Bipolar Interaction (MCBI)	p. 21
2.5 Simulation Techniques for Neutron-Induced Soft Error	p. 23
2.5.1 Overall Microscopic Soft-Error Model	p. 23
2.5.2 Nuclear Spallation Reaction Models	p. 24
2.5.3 Charge Deposition Model	p. 24
2.5.4 SRAM Device Model	p. 26
2.5.5 Cell Matrix Model	p. 27
2.5.6 Recycle Simulation Method	p. 28
2.5.7 Validation of SRAM Model	p. 29
2.6 Prediction for Scaling Effects Down to 22 nm Design Rule in SRAMs	p. 29
2.6.1 Roadmap Assumption	p. 29
2.6.2 Results and Discussions	p. 30
2.6.3 Validity of Simulated Results	p. 39
2.7 SER Estimation in Devices/Components/System	p. 40
2.7.1 Standards for SER Measurement for Memories	p. 40
2.7.2 Revisions Needed for the Standards	p. 40
2.7.3 Quantification of SER in Logic Devices and Related Issues	p. 42
2.8 An Example of Chip/Board-Level SER Measurement and Architectural Mitigation Techniques	p. 43
2.8.1 SER Test Procedures for Network Components	p. 43
2.8.2 Results and Discussions	p. 49
2.9 Hierarchical Mitigation Strategies	p. 51
2.9.1 Basic Three Approaches	p. 51
2.9.2 Design on the Upper Bound (DOUB)	p. 52
2.10 Inter Layer Built-in Reliability (LABIR)	p. 56
2.11 Summary	p. 57
References	p. 59
3 Electromagnetic Compatibility	p. 65
3.1 Introduction	p. 65
3.2 Quantitative Estimation of the EMI Radiation Based on the Measured Near-Field Magnetic Distribution	p. 68
3.2.1 Measurement of the Magnetic Field Distribution Near the Circuit Board	p. 68
3.2.2 Calculation of the Electric Current Distribution on the Circuit Board	p. 68
3.2.3 Calculation of the Far-Field Radiated EMI	p. 70
3.3 Development of a Non-contact Current Distribution Measurement Technique for LSI Packaging on PCBs	p. 71
3.3.1 Electric Current Distribution Detection	p. 71
3.3.2 The Current Detection Result and Its Verification	p. 74
3.4 Reduction Technique of Radiated Emission from Chassis with PCB	p. 75
3.4.1 Far-Field Measurement of Chassis with PCB	p. 75
3.4.2 Measurements of Junction Current	p. 79
3.4.3 PSPICE Modeling	p. 80
3.4.4 Experimental Validation	p. 85
3.5 Chapter Summary	p. 86
References	p. 88
4 Power Integrity	p. 91
4.1 Introduction	p. 91
4.2 Detrimental Effect and Technical Trends of Power Integrity Design of Electronic Systems and Devices	p. 92
4.2.1 Detrimental Effect by Power Supply Noise on Semiconducting Devices	p. 92
4.2.2 Trends of Power Supply Voltage and Power Supply Current for CMOS Semiconducting Devices	p. 98
4.2.3 Trend of Power Distribution Network Design for Electronic Systems	p. 100
4.3 Design Methodology of Power Integrity	p. 102
4.3.1 Definition of Power Supply Noise in Electric System	p. 102
4.3.2 Time-Domain and Frequency-Domain Design Methodology	p. 104
4.4 Modeling and Design Methodologies of PDS	p. 115
4.4.1 Modeling of Electrical Circuit Parameters	p. 116
4.4.2 Design Strategies of PDS	p. 121
4.5 Simultaneous Switching Noise (SSN)	p. 125
4.5.1 Principle of SSN	p. 126
4.5.2 S-G loop SSN	p. 127
4.5.3 P-G loop SSN	p. 129
4.6 Measurement of Power Distribution System Performance	p. 131
4.6.1 On-Chip Voltage Waveform Measurement	p. 131
4.6.2 On-Chip Power Supply Impedance Measurement	p. 137
4.7 Summary	p. 140
References	p. 141
5 Fault-Tolerant System Technology	p. 143
5.1 Introduction	p. 143
5.2 Metrics for Dependability	p. 144
5.2.1 Reliability	p. 144
5.2.2 Availability	p. 145
5.2.3 Safety	p. 147
5.3 Reliability Paradox	p. 148
5.4 Survey on Fault-Tolerant Systems	p. 150
5.5 Technical Issues	p. 153
5.5.1 High Performance	p. 154
5.5.2 Transparency	p. 156
5.5.3 Physical Transparency	p. 156
5.5.4 Fault Tolerance of Fault Tolerance for Ultimate Safety	p. 157
5.5.5 Reliability of Software	p. 160
5.6 Industrial Approach	p. 161
5.6.1 Autonomous Decentralized Systems	p. 163
5.6.2 Space Application	p. 164
5.6.3 Commercial Fault-Tolerant Systems	p. 164
5.6.4 Ultra-Safe System	p. 165
5.7 Availability Improvement vs. Coverage Improvement	p. 166
5.8 Trade-Off Between Availability and Coverage - Stepwise Negotiating Voting	p. 166
5.8.1 Basic Concept	p. 166
5.8.2 Hiten Onboard Computer	p. 169
5.8.3 Fault-Tolerance Experiments	p. 170
5.8.4 Extension of SNV - Redundancy Management	p. 173
5.9 Coverage Improvement	p. 175
5.9.1 Self-Checking Comparator	p. 176
5.9.2 Optimal Time Diversity	p. 179
5.10 On-Chip Redundancy	p. 184
5.11 High Performance (Commercial Fault-Tolerant Computer)	p. 188
5.11.1 Basic Concepts of TPR Architecture	p. 188
5.11.2 System Configuration	p. 189
5.11.3 System Reconfiguration on Fault Occurrence	p. 191
5.11.4 Processing Take-Over on Fault Occurrence	p. 191
5.11.5 Fault Tolerance of Fault Tolerance	p. 192
5.11.6 Commercial Product Model	p. 195
5.12 Current Application Field: X-by-Wire	p. 196
References	p. 198
6 Challenges in the Future	p. 201
References	p. 202
Index	p. 203

Available:*

On Order

Summary

Summary

Table of Contents